公开(公告)号：US06063653A

公开(公告)日：2000-05-16

申请号：US111279

申请日：1998-07-07

Applicant: Kang-Cheng Lin ,  Gwo-Long Lin

Inventor： Kang-Cheng Lin ,  Gwo-Long Lin

IPC: G03F7/20 ,  H01L21/336 ,  H01L21/84

CPC classification number: G03F7/2022 ,  H01L29/66765

Abstract: The present invention includes patterning a metal layer on a glass substrate. A dielectric layer is formed on the metal layer. An amorphous silicon layer is subsequently formed on the dielectric layer. A first positive photoresist is formed on the amorphous silicon layer. Then, a back-side exposure is used by using the gate electrodes as a mask. A bake step is performed to expand the lower portion of the photoresist. Next, a second positive photoresist layer is formed on the amorphous silicon layer and the residual first positive photoresist layer. A further back-side exposure is employed again from the back side of the substrate using the gate electrode as the mask. A second back step is applied to expand the lower portion of the second positive photoresist layer. An ion implantation is performed by using the second positive photoresist as a mask. Next, the substrate is then annealed. Amorphous silicon layer is then patterned. A further dielectric layer for isolation is formed on the patterned amorphous silicon layer. Source and drain are patterned on the dielectric layer to contact with the amorphous silicon layer. Subsequently, a passivation layer is deposited on the source and drain.

Abstract translation: 本发明包括在玻璃基板上图案化金属层。 在金属层上形成电介质层。 随后在电介质层上形成非晶硅层。 在非晶硅层上形成第一正性光致抗蚀剂。 然后，通过使用栅电极作为掩模来使用背面曝光。 进行烘烤步骤以扩展光致抗蚀剂的下部。 接下来，在非晶硅层和残留的第一正性光致抗蚀剂层上形成第二正性光致抗蚀剂层。 使用栅极电极作为掩模，再次从衬底的背面再次进行背面曝光。 应用第二后续步骤来扩展第二正性光致抗蚀剂层的下部。 通过使用第二正性光致抗蚀剂作为掩模来进行离子注入。 接着，将基板退火。 然后将非晶硅层图案化。 在图案化的非晶硅层上形成用于隔离的另外的电介质层。 源极和漏极在电介质层上被图案化以与非晶硅层接触。 随后，钝化层沉积在源极和漏极上。

公开(公告)号：US5834071A

公开(公告)日：1998-11-10

申请号：US802344

申请日：1997-02-11

Applicant: Kang-Cheng Lin

Inventor： Kang-Cheng Lin

IPC: H01L21/20 ,  H01L21/336 ,  H01L29/786 ,  B05D3/06

CPC classification number: H01L29/66765 ,  H01L21/2026 ,  H01L29/78675

Abstract: Method for forming a polycrystalline silicon (ploy-Si) film of a semiconductor device includes forming the gate electrode on a substrate and depositing a dielectric layer on the substrate and the conductive layer. Then a first layer (microcrystalline silicon:.mu.c-Si) is formed on the dielectric layer and a second layer (hydrogenated amorphous silicon:a-Si:H) is deposited on the first layer. Noted that the polycrystalline silicon (poly-Si) can be fabricated by applying the laser annealing to the first layer and the second layer to transform them to poly-Si. Annealing the first layer and the second layer by laser, followed by fabricating the source and drain electrodes, thus the TFT with good electrical characteristics is fabricated.

Abstract translation: 用于形成半导体器件的多晶硅（合金-Si）膜的方法包括在衬底上形成栅电极并在衬底和导电层上沉积电介质层。 然后在电介质层上形成第一层（微晶硅:μc-Si），在第一层上沉积第二层（氢化非晶硅：a-Si：H）。 注意到可以通过对第一层和第二层施加激光退火来将其转变成多晶硅来制造多晶硅（poly-Si）。 通过激光退火第一层和第二层，随后制造源极和漏极，由此制造具有良好电特性的TFT。

公开(公告)号：US20120273024A1

公开(公告)日：2012-11-01

申请号：US13240860

申请日：2011-09-22

Applicant: Chu-Jung Ko ,  Kang-Cheng LIN

Inventor： Chu-Jung Ko ,  Kang-Cheng LIN

IPC: H01L31/052 ,  H01L31/0232

CPC classification number: H01L31/056 ,  Y02E10/52

Abstract: A solar cell module includes lower and upper substrates that are spaced apart from each other, a plurality of spaced apart solar cells, a plurality of gratings, and a light-transmissive encapsulant disposed between the lower and upper substrates to encapsulate the solar cells and the gratings. Each of the gratings has a grating center, and four reflecting regions formed around the grating center. Each of the reflecting regions has a light entrance face that has a plurality of valleys and peaks. The valleys and peaks alternate with each other along a direction from the grating center to a corresponding one of the corners of a corresponding one of the four adjacent solar cells.

Abstract translation: 太阳能电池模块包括彼此间隔开的下部和上部基板，多个间隔开的太阳能电池，多个光栅以及设置在下部和上部基板之间的透光密封剂，以封装太阳能电池和 光栅。 每个光栅具有光栅中心，并且在光栅中心周围形成四个反射区域。 每个反射区域具有具有多个谷和峰的光入射面。 谷和峰沿着从光栅中心到四个相邻的太阳能电池中的对应的一个的角的相应一个方向彼此交替。

公开(公告)号：US20110117734A1

公开(公告)日：2011-05-19

申请号：US13014548

申请日：2011-01-26

Applicant: Da-Yuan Lee ,  Chien-Hao Huang ,  Chi-Chun Chen ,  Kang-Cheng Lin

Inventor： Da-Yuan Lee ,  Chien-Hao Huang ,  Chi-Chun Chen ,  Kang-Cheng Lin

IPC: H01L21/28

CPC classification number: H01L29/513 ,  H01L21/823828 ,  H01L29/4966 ,  H01L29/518

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate, and a transistor formed in the substrate. The transistor has a gate structure that includes an interfacial layer formed on the substrate, a high-k dielectric layer formed on the interfacial layer, a capping layer formed on the high-k dielectric layer, the capping layer including a silicon oxide, silicon oxynitride, silicon nitride, or combinations thereof, and a polysilicon layer formed on the capping layer.

Abstract translation: 本公开提供了一种半导体器件，其包括半导体衬底和形成在衬底中的晶体管。 晶体管具有栅极结构，该栅极结构包括形成在衬底上的界面层，形成在界面层上的高k电介质层，形成在高k电介质层上的覆盖层，覆盖层包括氧化硅，氮氧化硅 ，氮化硅或其组合，以及形成在覆盖层上的多晶硅层。

公开(公告)号：US20100044800A1

公开(公告)日：2010-02-25

申请号：US12589421

申请日：2009-10-23

Applicant: Joshua Tseng ,  Kang-Cheng Lin ,  Ji-Yi Yang ,  Kuo-Tai Huang ,  Ryan Chia-Jen Chen

Inventor： Joshua Tseng ,  Kang-Cheng Lin ,  Ji-Yi Yang ,  Kuo-Tai Huang ,  Ryan Chia-Jen Chen

IPC: H01L27/092

CPC classification number: H01L21/823857 ,  H01L21/823842

Abstract: A metal gate/high-k dielectric semiconductor device provides an NMOS gate structure and a PMOS gate structure formed on a semiconductor substrate. The NMOS gate structure includes a high-k gate dielectric treated with a dopant impurity such as La and the high-k gate dielectric material of the PMOS gate structure is deficient of this dopant impurity and further includes a work function tuning layer over the high-k gate dielectric.

Abstract translation: 金属栅极/高k电介质半导体器件提供形成在半导体衬底上的NMOS栅极结构和PMOS栅极结构。 NMOS栅极结构包括用诸如La的掺杂剂杂质处理的高k栅极电介质，并且PMOS栅极结构的高k栅极电介质材料缺乏该掺杂杂质，并且还包括高功率调制层， k栅极电介质。

公开(公告)号：US07625791B2

公开(公告)日：2009-12-01

申请号：US11926830

申请日：2007-10-29

Applicant: Joshua Tseng ,  Kang-Cheng Lin ,  Ji-Yi Yang ,  Kuo-Tai Huang ,  Ryan Chia-Jen Chen

Inventor： Joshua Tseng ,  Kang-Cheng Lin ,  Ji-Yi Yang ,  Kuo-Tai Huang ,  Ryan Chia-Jen Chen

IPC: H01L21/8238

CPC classification number: H01L21/823857 ,  H01L21/823842

Abstract: A metal gate/high-k dielectric semiconductor device provides an NMOS gate structure and a PMOS gate structure formed on a semiconductor substrate. The NMOS gate structure includes a high-k gate dielectric treated with a dopant impurity such as La and the high-k gate dielectric material of the PMOS gate structure is deficient of this dopant impurity and further includes a work function tuning layer over the high-k gate dielectric. A process for simultaneously forming the NMOS and PMOS gate structures includes forming the high-k gate dielectric material, and the work function tuning layer thereover, then selectively removing the work function tuning layer from the NMOS region and carrying out a plasma treatment to selectively dope the high-k gate dielectric material in the NMOS region with a dopant impurity while the high-k gate dielectric in the PMOS region is substantially free of the dopant impurity.

Abstract translation: 金属栅极/高k电介质半导体器件提供形成在半导体衬底上的NMOS栅极结构和PMOS栅极结构。 NMOS栅极结构包括用诸如La的掺杂剂杂质处理的高k栅极电介质，并且PMOS栅极结构的高k栅极电介质材料缺乏该掺杂杂质，并且还包括高功率调制层， k栅极电介质。 用于同时形成NMOS和PMOS栅极结构的工艺包括在其上形成高k栅极介电材料和功函数调谐层，然后从NMOS区选择性地去除功函数调谐层，并进行等离子体处理以选择性地掺杂 具有掺杂剂杂质的NMOS区域中的高k栅极电介质材料，而PMOS区域中的高k栅极电介质基本上不含掺杂剂杂质。

公开(公告)号：US20080173947A1

公开(公告)日：2008-07-24

申请号：US11656711

申请日：2007-01-23

Applicant: Yong-Tian Hou ,  Peng-Fu Hsu ,  Jin Ying ,  Kang-Cheng Lin ,  K. T. Huang ,  Tze-Liang Lee

Inventor： Yong-Tian Hou ,  Peng-Fu Hsu ,  Jin Ying ,  Kang-Cheng Lin ,  K. T. Huang ,  Tze-Liang Lee

IPC: H01L27/092

CPC classification number: H01L21/823842 ,  H01L21/28044 ,  H01L21/28088 ,  H01L21/823835 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7843

Abstract: A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a first MOS device of a first conductivity type and a second MOS device of a second conductivity type opposite the first conductivity type. The first MOS device includes a first gate dielectric on a semiconductor substrate; a first metal-containing gate electrode layer over the first gate dielectric; and a silicide layer over the first metal-containing gate electrode layer. The second MOS device includes a second gate dielectric on the semiconductor substrate; a second metal-containing gate electrode layer over the second gate dielectric; and a contact etch stop layer having a portion over the second metal-containing gate electrode layer, wherein a region between the portion of the contact etch stop layer and the second metal-containing gate electrode layer is substantially free from silicon.

Abstract translation: 提供半导体结构及其形成方法。 半导体结构包括第一导电类型的第一MOS器件和与第一导电类型相反的第二导电类型的第二MOS器件。 第一MOS器件包括在半导体衬底上的第一栅极电介质; 在所述第一栅极电介质上的第一含金属的栅电极层; 以及位于第一含金属栅电极层上的硅化物层。 第二MOS器件包括半导体衬底上的第二栅极电介质; 在所述第二栅极电介质上方的第二含金属的栅电极层; 以及具有位于所述第二含金属栅电极层上的部分的接触蚀刻停止层，其中所述接触蚀刻停止层的所述部分和所述第二含金属栅电极层之间的区域基本上不含硅。

公开(公告)号：US20070018279A1

公开(公告)日：2007-01-25

申请号：US11186581

申请日：2005-07-21

Applicant: Jian-Hong Lin ,  Kang-Cheng Lin ,  Tzu-Li Lee

Inventor： Jian-Hong Lin ,  Kang-Cheng Lin ,  Tzu-Li Lee

IPC: H01L29/00

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure prevents energy that is used to blow a fuse from causing damage. The semiconductor structure includes a device, guard ring, and at least one protection layer. The device is constructed on the semiconductor substrate underneath the fuse. The seal ring, which surrounds the fuse, is constructed on at least one metal layer between the device and the fuse for confining the energy therein. The protection layer is formed within the seal ring, on at least one metal layer between the device and the fuse for shielding the device from being directly exposed to the energy.

Abstract translation: 半导体结构防止用于熔断保险丝的能量造成损坏。 半导体结构包括器件，保护环和至少一个保护层。 该器件构造在保险丝下方的半导体衬底上。 围绕熔丝的密封环构造在设备和保险丝之间的至少一个金属层上，以将能量限制在其中。 保护层形成在密封环内，在设备和保险丝之间的至少一个金属层上，用于屏蔽器件不会直接暴露于能量。

公开(公告)号：US20060226507A1

公开(公告)日：2006-10-12

申请号：US11091508

申请日：2005-03-29

Applicant: Jian-Hong Lin ,  Kang-Cheng Lin

Inventor： Jian-Hong Lin ,  Kang-Cheng Lin

IPC: H01L29/00

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A laser fuse structure for a semiconductor device, the laser fuse structure having an array of laser fuses wherein one or more of the fuses in the array have a tortuous fuse line extending between first and second connectors that connect the fuse to an underlying circuit area.

Abstract translation: 一种用于半导体器件的激光熔丝结构，所述激光熔丝结构具有激光熔丝阵列，其中阵列中的一个或多个熔丝具有在将熔丝连接到下面的电路区域的第一和第二连接器之间延伸的曲折熔丝。

公开(公告)号：US06960496B2

公开(公告)日：2005-11-01

申请号：US10407095

申请日：2003-04-03

Applicant: Chao-Cheng Chen ,  Kang-Cheng Lin

Inventor： Chao-Cheng Chen ,  Kang-Cheng Lin

IPC: H01L21/332 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L23/58

CPC classification number: H01L23/585 ,  H01L21/76816 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of integrated circuit fabrication includes first forming at least one via in an insulting layer, and thereafter forming at least one trench-like structure separately. After a via is formed in an insulating layer, a layer of resist material is formed on the surface of the insulting layer and substantially filled the via. This step is followed by patterning at least one trench-like structure on the resist layer, and the trench-like structure is etched to the desired level. In some other embodiments, at least one trench-like structure is formed before at least one via is formed. An integrated circuit is manufactured by the aforementioned methods.

Abstract translation: 集成电路制造的方法包括首先在绝缘层中形成至少一个通孔，然后分开形成至少一个沟槽状结构。 在绝缘层中形成通孔之后，在绝缘层的表面上形成抗蚀材料层，并且基本上填充了通孔。 该步骤之后是在抗蚀剂层上图案化至少一个沟槽状结构，并且将沟槽状结构蚀刻到期望的水平。 在一些其它实施例中，在形成至少一个通孔之前形成至少一个沟槽状结构。 通过上述方法制造集成电路。