公开(公告)号：US09680245B2

公开(公告)日：2017-06-13

申请号：US14830019

申请日：2015-08-19

Applicant: R&D Circuits, Inc

Inventor： Thomas P Warwick ,  James V Russell ,  Demick McMullin ,  William Quick

IPC: H01R12/00 ,  H01R13/03 ,  H01R43/26 ,  H01R13/24 ,  H01R12/52

CPC classification number: H01R13/03 ,  H01R12/52 ,  H01R13/2414 ,  H01R43/26 ,  Y10T29/49208 ,  Y10T29/4921

Abstract: A method and an electrical interconnect mechanism in which elastomeric pins are printed onto metal retainer tabs having at least one protrusion or tab extending laterally therefrom to engage a catch or recess of the laminated housing so as to locate each of the elastomeric pins and secure them within the housing. In one embodiment a champher may be employed with a catch or recess to engagely secure a second protrusion or tab extending laterally from another side of said elastomeric pin. In another embodiment the elastomeric pin may have a solid metal ring or a slide collar around the center of the pin wherein the ring has one or two tabs for engaging the recess in the housing and if preferred also the recess of a champfer.

公开(公告)号：US20160065334A1

公开(公告)日：2016-03-03

申请号：US14833928

申请日：2015-08-24

Applicant: R&D Circuits, Inc.

Inventor： Thomas P. Warwick ,  James V. Russell

IPC: H04L1/24 ,  H04L12/26

CPC classification number: H04L1/243 ,  G01R31/2889 ,  H04L1/205 ,  H04L41/24 ,  H04L43/50 ,  H05K1/0231 ,  H05K1/185 ,  H05K2201/10015

Abstract: A method and a structure with multiple implementations is provided that depends on the specific need, for placing (embedding) a serial loopback circuit of known design in a printed circuit board directly beneath the device under test. Micro-vias and traces connect components including transmitter components (TX) and receiver components (RX) that are formed into a loopback circuit for connection to a device under test (DUT). The connection is accomplished by a coupling capacitor with a shortest possible electrical length approximating a straight line between said components and said DUT and said distance is a length of said short straight line times a square root of 2 so that said receiver components are beneath the DUT.

Abstract translation: 提供了具有多个实现的方法和结构，其取决于具体需要，将已知设计的串行回送电路放置（嵌入）在正在被测器件正下方的印刷电路板中。 微通孔和迹线连接组件，包括发射器组件（TX）和接收器组件（RX），其形成为用于连接到被测设备（DUT）的环回电路。 该连接由耦合电容器实现，其具有近似于所述部件和所述DUT之间的直线的最短电长度，并且所述距离是所述短直线的长度乘以2的平方根，使得所述接收器部件在DUT下方 。

公开(公告)号：US20250085332A1

公开(公告)日：2025-03-13

申请号：US18958656

申请日：2024-11-25

Applicant: R & D Circuits, Inc.

Inventor： Donald Thompson ,  Thomas Smith

IPC: G01R31/28 ,  G01R31/70 ,  H05K3/00 ,  H05K3/42

Abstract: A method for detecting failed back-drills in PCBs in the process of fabricating a PCB so that the failed back-drill can be screened out or repaired. A short to ground connection is added for every back-drill via that will be cut when the back-drill removes the via stub. If the back-drill is bad or failed the short to ground will fail the subsequent electrical tests. The PCB can be repaired by re-drilling the hole or via. Failed back-drills may be detected in the manufacturing stage using standard equipment and test procedures. This process creates a simple pass-fail measurement that uses an existing common test process to catch failed back drills in the PCB fabrication facility. This allows for easy and cost-effective repair and guarantees back-drill failures do not pass into the field.

公开(公告)号：US20230026067A1

公开(公告)日：2023-01-26

申请号：US17381757

申请日：2021-07-21

Applicant: R&D Circuits

Inventor： Michael Caprio ,  Dwarkesh Patel ,  Hiren Patel ,  Yubing Wong ,  Donald Eric Thompson

IPC: G01R31/28 ,  H05K3/00 ,  H05K3/42

Abstract: The present invention provides a method for detecting and adjusting failed back-drills in PCBs in the process of fabricating a PCB so that the failed back-drill can be screened out or repaired. This is accomplished, by after detecting poor back drills in a PCB, measuring the actual thickness of each PCB board. Next, the measured actual thickness of each PCB board is compared with .the theoretical thickness of each PCB board. The back drill depth for each area of the PCB board is then adjusted for its theoretical thickness and percent variation from the measured thickness.to adjust the poor back drill.

公开(公告)号：US20190141840A1

公开(公告)日：2019-05-09

申请号：US16051772

申请日：2018-08-01

Applicant: R&D Circuits, Inc.

Inventor： Donald Eric Thompson ,  Dhananjaya Turpuseema

IPC: H05K3/42 ,  H05K3/46 ,  H05K1/11

Abstract: A method and structure that forms a PCB while removing or eliminating a stub from a via without back-drilling or doing multi-laminations. In the preferred embodiment, the printed circuit board includes a via extending through a plurality of stacked layers. The via includes a plated through hole that is connected to at least two other metalized layers. There is a portion of the via that is extraneous and that has a negative performance on the functionality of the printed circuit board. The single lamination buried via method adds a seed layer resist that prevents an electrical connection during electroplating thus preventing the via from metalizing where it is not desired.

公开(公告)号：US20180033748A1

公开(公告)日：2018-02-01

申请号：US15151658

申请日：2016-05-11

Applicant: R&D CIRCUITS, INC.

Inventor： JAMES V. RUSSELL

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L21/4853 ,  G01R1/07378 ,  H01L21/56 ,  H01L23/49811 ,  H01L23/49838

Abstract: The present invention relates to a method and an apparatus for a resurfaceable contact pad that uses an epoxy to encapsulate contact pads so that the epoxy and encapsulated contact pads are coplanar on a silicon redistribution interposer. These redistribution interposers electrically connect a wafer semi-conductor to a probe card where it is necessary to convert the course pad arrangement of one with a fine pad arrangement of the other through the use of an interposer board. The present invention relates to an apparatus and a method creates resurfaceable contact pads which may be resurfaced one or multiple times with an abrasive sanding operation to recreate a coplanar surface should any contact pad surfaces become damaged, allowing for a more cost-effective repair.

公开(公告)号：US20150372408A1

公开(公告)日：2015-12-24

申请号：US14830019

申请日：2015-08-19

Applicant: R&D Circuits, Inc

Inventor： Thomas P. Warwick ,  James V. Russell ,  Demick McMullin ,  William Quick

IPC: H01R13/03 ,  H01R43/26

CPC classification number: H01R13/03 ,  H01R12/52 ,  H01R13/2414 ,  H01R43/26 ,  Y10T29/49208 ,  Y10T29/4921

Abstract: A method and an electrical interconnect mechanism in which elastomeric pins are printed onto metal retainer tabs having at least one protrusion or tab extending laterally therefrom to engage a catch or recess of the laminated housing so as to locate each of the elastomeric pins and secure them within the housing. In one embodiment a champher may be employed with a catch or recess to engagely secure a second protrusion or tab extending laterally from another side of said elastomeric pin. In another embodiment the elastomeric pin may have a solid metal ring or a slide collar around the center of the pin wherein the ring has one or two tabs for engaging the recess in the housing and if preferred also the recess of a champfer.

Abstract translation: 一种方法和电互连机构，其中弹性销被印刷到具有至少一个从其横向延伸的突起或突片的金属保持器突片上，以接合层叠壳体的卡扣或凹部，以便定位每个弹性销并将其固定在 住房。 在一个实施例中，可以使用带有卡扣或凹槽的凸轮来接合地固定从所述弹性销的另一侧横向延伸的第二突起或突出部。 在另一个实施例中，弹性体销可以具有围绕销的中心的实心金属环或滑动环，其中环具有用于接合壳体中的凹部的一个或两个突出部以及冠状器的凹部。

公开(公告)号：US20140268613A1

公开(公告)日：2014-09-18

申请号：US14120152

申请日：2014-04-30

Applicant: R&D Circuits,Inc.

Inventor： James V. Russell

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K3/30 ,  G01R1/07378 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/50 ,  H01L24/13 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/14 ,  H05K1/0213 ,  H05K1/0231 ,  H05K1/0234 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/141 ,  H05K1/185 ,  H05K2201/049 ,  H05K2201/10378 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/4913 ,  H01L2924/00

Abstract: Embedding a power modification component such as a capacitance inside of an adaptor board located to extend over and beyond the vias of the main circuit board so that a portion of the interposer board containing the embedded capacitance is located beyond where the vias or blinds are located. This permits that via to conduct through the opening. In this way, the capacitance and the resistance will have a closer contact point to the electrical component. A resistance can also be embedded in an opening in the adaptor board and be vertically aligned within the opening to make contact with a pad on top of the adaptor board and a pad at the bottom of the adaptor board so that electricity conducts through the embedded component.

Abstract translation: 将诸如电容内部的功率改进组件嵌入到位于主电路板的通孔之上延伸超过主电路板的通孔的电容器内，使得包含嵌入电容的插入板的部分位于通孔或百叶窗所在的位置之外。 这允许via通过开放。 以这种方式，电容和电阻将具有与电气部件更接近的接触点。 电阻也可以嵌入到适配器板的开口中并且在开口内垂直对准以与适配器板的顶部上的焊盘接触并且在适配器板的底部具有焊盘，使得电通过嵌入部件 。

公开(公告)号：US20230180397A1

公开(公告)日：2023-06-08

申请号：US17542867

申请日：2021-12-06

Applicant: R&D Circuits

Inventor： Donald Eric Thompson

IPC: H05K3/42 ,  H05K3/00 ,  H05K3/36 ,  H05K1/18 ,  H05K1/02 ,  C25D7/00 ,  C25D3/38 ,  C25D5/02

CPC classification number: H05K3/426 ,  H05K3/0047 ,  H05K3/368 ,  H05K1/182 ,  H05K1/0222 ,  C25D7/00 ,  C25D3/38 ,  C25D5/02 ,  H05K2201/10325 ,  H05K2201/09072 ,  H05K2201/09545 ,  H05K2203/0723 ,  H05K2201/10409 ,  H05K2201/10303

Abstract: The present invention provides a novel method of constructing a coax spring-pin socket that furnishes better performance and is easier to manufacture in volume using common dielectrics and copper plating. This is accomplished by, in application, a lamination of PCB dielectric layers. This dielectric block is then drilled, plated, etched, and drilled in steps for the construction of a coaxial structure for the signal pins, and a ground structure for ground pins. This design process that can be quickly adjusted and customized for each design.