公开(公告)号：US12153084B2

公开(公告)日：2024-11-26

申请号：US17173441

申请日：2021-02-11

Applicant: R & D Circuits, Inc.

Inventor： Donald Eric Thompson ,  Thomas Smith

IPC: G01R31/28 ,  G01R31/70 ,  H05K3/00 ,  H05K3/42

Abstract: A method for detecting failed back-drills in PCBs in the process of fabricating a PCB so that the failed back-drill can be screened out or repaired. short to ground connection is added for every back-drill via that will be cut when the back-drill removes the via stub. If the back-drill is bad or failed the short to ground will fail the subsequent electrical tests. The PCB can be repaired by re-drilling the hole or via. Failed back-drills may be detected in the manufacturing stage using standard equipment and test procedures. This process creates a simple pass-fail measurement that uses an existing common test process to catch failed back drills in the PCB fabrication facility. This allows for easy and cost-effective repair and guarantees back-drill failures do not pass into the field.

公开(公告)号：US20180068867A1

公开(公告)日：2018-03-08

申请号：US15688238

申请日：2017-08-28

Applicant: R&D CIRCUITS, INC.

Inventor： Donald Thompson ,  Cosimo Cantatore

IPC: H01L21/48 ,  H01R12/70 ,  H01R12/52 ,  H01R13/11 ,  H01R13/24

CPC classification number: H01L21/486 ,  B33Y80/00 ,  G01R1/0483 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/16227 ,  H01L2224/1623 ,  H01L2224/16235 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01R12/52 ,  H01R12/7082 ,  H01R13/112 ,  H01R13/2414 ,  H05K1/092 ,  H05K3/4069 ,  H05K7/1061 ,  H05K2203/107 ,  H05K2203/1131

Abstract: The present invention provides for a structure and a mechanism by which by utilizing additive manufacturing processes electrical connections are created that connect the top and bottom of a block in a customizable pattern. Specifically connection points can be created on the surface of the block and route them to alternate locations transforming the original pattern to a smaller, larger, or alternate pattern.

公开(公告)号：US12135347B2

公开(公告)日：2024-11-05

申请号：US17381757

申请日：2021-07-21

Applicant: R&D Circuits

Inventor： Michael Caprio ,  Dwarkesh Patel ,  Hiren Patel ,  Yubing Wang ,  Donald Eric Thompson

IPC: G01R31/28 ,  H05K3/00 ,  H05K3/42 ,  H05K1/02 ,  H05K1/11

Abstract: The present invention provides a method for detecting and adjusting failed back-drills in PCBs in the process of fabricating a PCB so that the failed back-drill can be screened out or repaired. This is accomplished, by after detecting poor back drills in a PCB, measuring the actual thickness of each PCB board. Next, the measured actual thickness of each PCB board is compared with .the theoretical thickness of each PCB board. The back drill depth for each area of the PCB board is then adjusted for its theoretical thickness and percent variation from the measured thickness to adjust the poor back drill.

公开(公告)号：US12052830B2

公开(公告)日：2024-07-30

申请号：US17542867

申请日：2021-12-06

Applicant: R&D Circuits

Inventor： Donald Eric Thompson

IPC: H05K3/42 ,  C25D3/38 ,  C25D5/02 ,  C25D7/00 ,  H05K1/02 ,  H05K1/18 ,  H05K3/00 ,  H05K3/36

CPC classification number: H05K3/426 ,  C25D3/38 ,  C25D5/02 ,  C25D7/00 ,  H05K1/0222 ,  H05K1/182 ,  H05K3/0047 ,  H05K3/368 ,  H05K2201/09072 ,  H05K2201/09545 ,  H05K2201/10303 ,  H05K2201/10325 ,  H05K2201/10409 ,  H05K2203/0723

Abstract: The present invention provides a novel method of constructing a coax spring-pin socket that furnishes better performance and is easier to manufacture in volume using common dielectrics and copper plating. This is accomplished by, in application, a lamination of PCB dielectric layers. This dielectric block is then drilled, plated, etched, and drilled in steps for the construction of a coaxial structure for the signal pins, and a ground structure for ground pins. This design process that can be quickly adjusted and customized for each design.

公开(公告)号：US10559476B2

公开(公告)日：2020-02-11

申请号：US15688238

申请日：2017-08-28

Applicant: R&D Circuits, Inc.

Inventor： Donald Thompson ,  Cosimo Cantatore

IPC: H01L21/48 ,  H01R12/52 ,  H01R12/70 ,  H01R13/11 ,  H01R13/24

Abstract: The present invention provides for a structure and a mechanism by which by utilizing additive manufacturing processes electrical connections are created that connect the top and bottom of a block in a customizable pattern. Specifically connection points can be created on the surface of the block and route them to alternate locations transforming the original pattern to a smaller, larger, or alternate pattern.

公开(公告)号：US10257930B2

公开(公告)日：2019-04-09

申请号：US15189435

申请日：2016-06-22

Applicant: R&D CIRCUITS, INC.

Inventor： Thomas P Warwick ,  Dhananjaya Trupuseema ,  James V Russell

IPC: H01R43/00 ,  H05K1/11 ,  H05K3/40 ,  H05K3/10 ,  H05K3/32 ,  H05K1/09 ,  H05K1/02 ,  H05K1/18

Abstract: The present invention provides for a method and structure for forming three-dimensionally routed dielectric wires between discrete points on the two or more parallel circuit planes. The wires may be freely routed in three-dimensional space as to create the most efficient routing between the two arbitrarily defined points on the two or more parallel circuit planes. Metalizing the outer surfaces of these three dimensional dielectric wires electrically coupling the discrete wires to their respective discrete contact points. Two or more of these wires may be in intimate contact to one another electrically coupling to each other as well as to two or more discrete contact pads. These electrically coupled contact pads may be on opposite sides or on the same side of the structure and the formed metalized wires may originate on one side and terminate on the other or originate and terminate from the same side.

公开(公告)号：US20170374739A1

公开(公告)日：2017-12-28

申请号：US15189435

申请日：2016-06-22

Applicant: R&D CIRCUITS, INC.

Inventor： THOMAS P. WARWICK ,  DHANANJAYA TRUPUSEEMA ,  JAMES V. RUSSELL

IPC: H05K1/11 ,  H05K1/09 ,  H05K1/18 ,  H05K1/02 ,  H05K3/10 ,  H05K3/32 ,  H05K3/40

CPC classification number: H05K1/111 ,  H01L21/486 ,  H01L23/49827 ,  H01R13/2435 ,  H05K1/0251 ,  H05K1/0296 ,  H05K1/09 ,  H05K1/118 ,  H05K1/18 ,  H05K3/10 ,  H05K3/32 ,  H05K3/368 ,  H05K3/4007 ,  H05K3/4038 ,  H05K3/4046 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/1003 ,  H05K2201/10378

Abstract: The present invention provides for a method and structure for forming three-dimensionally routed dielectric wires between discrete points on the two or more parallel circuit planes. The wires may be freely routed in three-dimensional space as to create the most efficient routing between the two arbitrarily defined points on the two or more parallel circuit planes. Metalizing the outer surfaces of these three dimensional dielectric wires electrically coupling the discrete wires to their respective discrete contact points. Two or more of these wires may be in intimate contact to one another electrically coupling to each other as well as to two or more discrete contact pads. These electrically coupled contact pads may be on opposite sides or on the same side of the structure and the formed metalized wires may originate on one side and terminate on the other or originate and terminate from the same side

公开(公告)号：US20220252660A1

公开(公告)日：2022-08-11

申请号：US17173441

申请日：2021-02-11

Applicant: R & D Circuits, Inc.

Inventor： Donald Eric Thompson ,  Thomas Smith

IPC: G01R31/28 ,  G01R31/70 ,  H05K3/42 ,  H05K3/00

Abstract: The present invention provides a method for detecting failed back-drills in PCBs in the process of fabricating a PCB so that the failed back-drill can be screened out or repaired. The present invention accomplishes this by adding a short to ground connection for every back-drill via that will be cut when the back-drill removes the via stub. If the back-drill is bad or failed the short to ground will fail the subsequent electrical tests. The PCB can be repaired by re-drilling the hole or via. The present invention allows for detecting failed back-drills with easy detection in the manufacturing stage using standard equipment and test procedures. This process creates a simple pass-fail measurement that uses an existing common test process to catch failed back drills in the PCB fabrication facility. This allows for easy and cost-effective repair and guarantees back-drill failures do not pass into the field.

公开(公告)号：US20210376535A1

公开(公告)日：2021-12-02

申请号：US16887640

申请日：2020-05-29

Applicant: R&D Circuits, Inc.

Inventor： Donald Eric Thompson

IPC: H01R13/66 ,  H01R13/17 ,  G01R1/073

Abstract: The present invention provides for an improved method and structure for forming an electrical interconnects mechanism in a Power Distribution Network (PDN) by placing capacitors on the top of the pin array on the printed circuit board (PCB) of the structure to decouple the PDN and results in lower impedance benefitting the frequency range of the PDN effecting a significant performance improvement in the spring-pin inductance from the transmission line. This reduction in impedance reduces the power supply ripple.

公开(公告)号：US09978702B2

公开(公告)日：2018-05-22

申请号：US15151658

申请日：2016-05-11

Applicant: R&D CIRCUITS, INC.

Inventor： James V Russell

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L21/4853 ,  G01R1/07378 ,  H01L21/56 ,  H01L23/49811 ,  H01L23/49838

Abstract: The present invention relates to a method and an apparatus for a resurfaceable contact pad that uses an epoxy to encapsulate contact pads so that the epoxy and encapsulated contact pads are coplanar on a silicon redistribution interposer. These redistribution interposers electrically connect a wafer semi-conductor to a probe card where it is necessary to convert the course pad arrangement of one with a fine pad arrangement of the other through the use of an interposer board. The present invention relates to an apparatus and a method creates resurfaceable contact pads which may be resurfaced one or multiple times with an abrasive sanding operation to recreate a coplanar surface should any contact pad surfaces become damaged, allowing for a more cost-effective repair.