公开(公告)号：US10074559B1

公开(公告)日：2018-09-11

申请号：US15452394

申请日：2017-03-07

Applicant: APPLIED MATERIALS, INC.

Inventor： Geetika Bajaj ,  Tapash Chakraborty ,  Prerna Sonthalia Goradia ,  Robert Jan Visser ,  Bhaskar Kumar ,  Deenesh Padhi

IPC: H01L21/32 ,  H01L21/768

Abstract: Methods of discouraging poreseal deposition on metal (e.g. copper) at the bottom of a via during a poresealing process are described. A self-assembled monolayer (SAM) is selectively formed on the exposed metal surface and prevents or discourages formation of poreseal on the metal. The SAM is selectively formed by exposing a patterned substrate to a SAM molecule which preferentially binds to exposed metal surfaces rather than exposed dielectric surfaces. The selected SAM molecules tend to not bind to low-k films. The SAM and SAM molecule are also chosen so the SAM tolerates subsequent processing at relatively high processing temperatures above 140° C. or 160° C. Aliphatic or aromatic SAM molecules with thiol head moieties may be used to form the SAM.

公开(公告)号：US09984976B2

公开(公告)日：2018-05-29

申请号：US15041454

申请日：2016-02-11

Applicant: APPLIED MATERIALS, INC.

Inventor： Yana Cheng ,  Yong Cao ,  Srinivas Guggilla ,  Sree Rangasai Kesapragada ,  Xianmin Tang ,  Deenesh Padhi

IPC: H01L23/48 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  C23C14/0036 ,  C23C14/0676 ,  C23C14/352 ,  H01J37/32504 ,  H01J37/3408 ,  H01J37/3455 ,  H01L21/02145 ,  H01L21/02266 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/53223 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295

Abstract: Interconnect structures and methods of formation of such interconnect structures are provided herein. In some embodiments, a method of forming an interconnect includes: depositing a silicon-aluminum oxynitride (SiAlON) layer atop a first layer of a substrate, wherein the first layer comprises a first feature filled with a first conductive material; depositing a dielectric layer over the silicon-aluminum oxynitride (SiAlON) layer; and forming a second feature in the dielectric layer and the silicon-aluminum oxynitride (SiAlON) layer to expose the first conductive material.

公开(公告)号：US09793108B2

公开(公告)日：2017-10-17

申请号：US14750778

申请日：2015-06-25

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Mehul B. Naik ,  Deenesh Padhi ,  Priyanka Dash ,  Bhaskar Kumar ,  Alexandros T. Demos

IPC: H01L21/02 ,  H01L21/31 ,  C23C16/36 ,  H01L21/3105 ,  C23C16/04 ,  C23C16/48 ,  C23C16/56

CPC classification number: H01L21/02126 ,  C23C16/045 ,  C23C16/36 ,  C23C16/482 ,  C23C16/56 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02359 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831

Abstract: A method for sealing porous low-k dielectric films is provided. The method comprises exposing a substrate to UV radiation and a first reactive gas, wherein the substrate has an open feature defined therein, the open feature defined by a porous low-k dielectric layer and a conductive material, wherein the porous low-k dielectric layer is a silicon and carbon containing material and selectively forming a pore sealing layer in the open feature on exposed surfaces of the porous low-k dielectric layer using UV assisted photochemical vapor deposition.

公开(公告)号：US09646876B2

公开(公告)日：2017-05-09

申请号：US14634512

申请日：2015-02-27

Applicant: Applied Materials, Inc.

Inventor： Deenesh Padhi ,  Srinivas Guggilla ,  Alexandros T. Demos ,  Bhaskar Kumar ,  He Ren ,  Priyanka Dash

IPC: H01L21/44 ,  H01L21/768 ,  H01L21/02 ,  H01L23/532

CPC classification number: H01L21/76813 ,  H01L21/02458 ,  H01L21/76808 ,  H01L21/76831 ,  H01L21/76862 ,  H01L23/53295

Abstract: A method of forming features in a dielectric layer is described. A via, trench or a dual-damascene structure may be present in the dielectric layer prior to depositing a conformal aluminum nitride layer. The conformal aluminum nitride layer is configured to serve as a barrier to prevent diffusion across the barrier. The methods of forming the aluminum nitride layer involve the alternating exposure to two precursor treatments (like ALD) to achieve high conformality. The high conformality of the aluminum nitride barrier layer enables the thickness to be reduced and the effective conductivity of the subsequent gapfill metal layer to be increased.

公开(公告)号：US08993454B2

公开(公告)日：2015-03-31

申请号：US14028025

申请日：2013-09-16

Applicant: Applied Materials, Inc.

Inventor： Martin Jay Seamons ,  Sudha Rathi ,  Kwangduk Douglas Lee ,  Deenesh Padhi ,  Bok Hoen Kim ,  Chiu Chan

IPC: H01L21/64 ,  C23C16/02 ,  C23C16/26 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/64 ,  C23C16/0272 ,  C23C16/26 ,  H01L21/02115 ,  H01L21/02274 ,  H01L21/31144

Abstract: Embodiments of the present invention generally relate to the fabrication of integrated circuits and particularly to the deposition of a boron containing amorphous carbon layer on a semiconductor substrate. In one embodiment, a boron-containing amorphous carbon film is disclosed. The boron-containing amorphous carbon film comprises from about 10 to 60 atomic percentage of boron, from about 20 to about 50 atomic percentage of carbon, and from about 10 to about 30 atomic percentage of hydrogen.

Abstract translation: 本发明的实施例一般涉及集成电路的制造，特别涉及在半导体衬底上沉积含硼无定形碳层。 在一个实施方案中，公开了含硼无定形碳膜。 含硼无定形碳膜包含约10至60原子百分数的硼，约20至约50原子百分比的碳和约10至约30原子百分比的氢。

公开(公告)号：US20250149373A1

公开(公告)日：2025-05-08

申请号：US18545643

申请日：2023-12-19

Applicant: Applied Materials, Inc.

Inventor： Nitin Deepak ,  Jennifer Sun ,  Mayur Govind Kulkarni ,  Miguel S. Fung ,  Darius "D" Alexander-Jones ,  Chih Peng ,  Deenesh Padhi ,  Kwangduk Douglas Lee ,  Ganesh Balasubramanian ,  Juan Carlos Rocha-Alvarez ,  Simmon Kuo ,  Nagarajan Rajagopalan ,  Shankho Sen

IPC: H01L21/687

Abstract: Semiconductor components and systems having substrate contacting surfaces with a reduced hardness are provided. Systems and components include a ceramic, metallic, or non-metallic component for contacting a substrate. Systems and components include a layer of coating material on at least a portion of a substrate contacting surface of the component. Systems and components include where the component for contacting a substrate includes a component Vickers hardness value, and the layer of coating material exhibits a coating layer Vickers hardness value. Systems and components include where the coating layer Vickers hardness value is greater than or about 10% less than the component Vickers hardness value.

公开(公告)号：US20240420949A1

公开(公告)日：2024-12-19

申请号：US18210522

申请日：2023-06-15

Applicant: Applied Materials, Inc.

Inventor： Woongsik Nam ,  Euhngi Lee ,  Tianyang Li ,  Jisung Park ,  Hang Yu ,  Deenesh Padhi ,  Shichen Fu ,  Yufeng Jiang

IPC: H01L21/02

Abstract: Exemplary processing methods may include i) providing one or more deposition precursors to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. The substrate may include one or more features defining one or more sidewalls. The methods may include ii) forming plasma effluents of the one or more deposition precursors. The methods may include iii) contacting the substrate with the plasma effluents of the one or more deposition precursors. The contacting may deposit a doped silicon-and-oxygen-containing material on the substrate. A first portion of the doped silicon-and-oxygen-containing material deposited on the one or more sidewalls of the one or more features may be characterized by a poorer film quality than a second portion of the doped silicon-and-oxygen-containing material deposited on a lower portion of the one or more features.

公开(公告)号：US11948846B2

公开(公告)日：2024-04-02

申请号：US18130500

申请日：2023-04-04

Applicant: Applied Materials, Inc.

Inventor： Wenjiao Wang ,  Joshua Maher ,  Xinhai Han ,  Deenesh Padhi ,  Tza-Jing Gung

IPC: H01L21/66 ,  G03F7/00 ,  G06F30/398

CPC classification number: H01L22/12 ,  G06F30/398 ,  G03F7/705

Abstract: Methods and systems are described for generating assessment maps. A method includes receiving a first vector map comprising a first set of vectors each indicating a distortion of a particular location on a substrate and generating a second vector map indicating a change in direction of a magnitude of the distortion of the particular location on the substrate. The method further includes generating a third vector map comprising vectors reflecting reduced noise in distortions across the plurality of locations on the substrate and generating a fourth vector map projecting a direction component of each vector component in the third set of vectors to a radial direction. The method further includes generating a fifth vector map by grouping the vectors of the fourth set of vectors and determining a magnitude associated with each group of vectors.

公开(公告)号：US11869795B2

公开(公告)日：2024-01-09

申请号：US17371549

申请日：2021-07-09

Applicant: Applied Materials, Inc.

Inventor： Saketh Pemmasani ,  Akshay Dhanakshirur ,  Mayur Govind Kulkarni ,  Madhu Santosh Kumar Mutyala ,  Hang Yu ,  Deenesh Padhi

IPC: H01L21/683 ,  C23C16/458 ,  H01J37/32

CPC classification number: H01L21/6833 ,  C23C16/4586 ,  H01J37/32697 ,  H01J37/32724 ,  H01J2237/3321

Abstract: Exemplary substrate support assemblies may include a chuck body defining a substrate support surface. The substrate support surface may define a plurality of protrusions that extend upward from the substrate support surface. The substrate support surface may define an annular groove and/or ridge. A subset of the plurality of protrusions may be disposed within the annular groove and/or ridge. The substrate support assemblies may include a support stem coupled with the chuck body.

公开(公告)号：US20230411462A1

公开(公告)日：2023-12-21

申请号：US18460290

申请日：2023-09-01

Applicant: Applied Materials, Inc.

Inventor： Akhil Singhal ,  Allison Yau ,  Sang-Jin Kim ,  Zeqiong Zhao ,  Zhijun Jiang ,  Deenesh Padhi ,  Ganesh Balasubramanian

IPC: H01L21/28 ,  H01L29/423 ,  H01L21/3213 ,  H01L21/311

CPC classification number: H01L29/40114 ,  H01L21/31116 ,  H01L21/32137 ,  H01L29/42324

Abstract: Exemplary semiconductor structures and processing methods may include forming a first portion of a first semiconductor layer characterized by a first etch rate for an etch treatment, forming a second portion of the first semiconductor layer characterized by a second etch rate that is less than the first etch rate for the etch treatment, and forming a third portion of the first semiconductor layer characterized by a third etch rate that is greater than the second etch rate. The processing methods may further include etching an opening through the first semiconductor layer, where the opening has a height and a width, and where the opening is characterized by a variation in the width between a midpoint of the height of the opening and an endpoint of the opening that is less than or about 5 Å.