公开(公告)号：US20240136207A1

公开(公告)日：2024-04-25

申请号：US17971338

申请日：2022-10-20

Applicant: Applied Materials, Inc.

Inventor： Ala MORADIAN ,  Saurabh CHOPRA

IPC: H01L21/67

CPC classification number: H01L21/67115 ,  H01L21/67207

Abstract: The present disclosure relates to heat source arrangements, processing chambers, and related methods to facilitate deposition process adjustability. In one implementation, a processing chamber applicable for use in semiconductor manufacturing includes a lower window and an upper window. The lower window and the upper window at least partially define an internal volume. The processing chamber includes a substrate support disposed in the internal volume, and the substrate support includes a support face. The processing chamber includes one or more inner heat sources. Each inner heat source of the one or more inner heat sources is oriented substantially parallel to a surface of the support face. The processing chamber includes one or more outer heat sources disposed outwardly of the inner heat sources. Each outer heat source of the one or more outer heat sources is oriented nonparallel to the surface of the support face.

公开(公告)号：US20200283896A1

公开(公告)日：2020-09-10

申请号：US16784623

申请日：2020-02-07

Applicant: Applied Materials, Inc.

Inventor： Xuebin LI ,  Errol Antonio C. SANCHEZ ,  Saurabh CHOPRA

IPC: C23C16/455 ,  C23C16/02 ,  C23C16/06 ,  C23C16/24

Abstract: Methods for forming silicide materials and source/drain devices are provided. The methods and devices can include methods for forming silicide films, including metal silicide and metal germanide silicide films, on germanium-containing film, such as used as a pMOS layer in a source/drain contact region. In one or more embodiments, a method of processing a substrate includes positioning the substrate within a processing chamber, where the substrate contains one or more germanium-containing films, heating the substrate to a temperature of about 100° C. to about 600° C., and exposing the substrate to one or more metal precursors and one or more silicon precursors during a vapor deposition process and forming a silicide film on the germanium-containing film, where the silicide film has a conformality of about 1% to about 50% of an average thickness of the silicide film.

公开(公告)号：US20140106547A1

公开(公告)日：2014-04-17

申请号：US14133148

申请日：2013-12-18

Applicant: APPLIED MATERIALS, INC.

Inventor： Zhiyuan YE ,  Xuebin LI ,  Saurabh CHOPRA ,  Yihwan KIM

IPC: H01L21/02

CPC classification number: H01L21/02532 ,  H01L21/0257 ,  H01L21/02576 ,  H01L21/0262 ,  H01L29/1054 ,  H01L29/78

Abstract: Embodiments of the present invention generally relate to methods for forming silicon epitaxial layers on semiconductor devices. The methods include forming a silicon epitaxial layer on a substrate at increased pressure and reduced temperature. The silicon epitaxial layer has a phosphorus concentration of about 1×1021 atoms per cubic centimeter or greater, and is formed without the addition of carbon. A phosphorus concentration of about 1×1021 atoms per cubic centimeter or greater increases the tensile strain of the deposited layer, and thus, improves channel mobility. Since the epitaxial layer is substantially free of carbon, the epitaxial layer does not suffer from film formation and quality issues commonly associated with carbon-containing epitaxial layers.

Abstract translation: 本发明的实施例一般涉及在半导体器件上形成硅外延层的方法。 所述方法包括在增加的压力和降低的温度下在衬底上形成硅外延层。 硅外延层的磷浓度约为1×1021原子/立方厘米或更大，并且不添加碳形成。 大约1×1021原子/立方厘米或更大的磷浓度增加沉积层的拉伸应变，从而提高通道迁移率。 由于外延层基本上不含碳，外延层不会受到成膜和通常与含碳外延层相关的质量问题的影响。

公开(公告)号：US20240248297A1

公开(公告)日：2024-07-25

申请号：US18159208

申请日：2023-01-25

Applicant: Applied Materials, Inc.

Inventor： Ala MORADIAN ,  Saurabh CHOPRA ,  Lori D. WASHINGTON

IPC: G02B26/08 ,  G02B17/00 ,  H01L21/67 ,  H05B3/00

CPC classification number: G02B26/0816 ,  G02B17/002 ,  H01L21/67115 ,  H05B3/0047

Abstract: Embodiments herein are generally directed to electronic device manufacturing and, more particularly, to systems and methods for lamp heating in thermal processing chambers. In an embodiment, an adjustable reflector includes a plurality of reflector elements. Each of the plurality of elements as a first surface, a second surface, and a plurality of sidewalls. The first surface is a reflective surface and is configured to face a lamp. The adjustable reflector includes one or more actuation mechanisms coupled to the plurality of elements. A method of thermally processing a substrate includes measuring a thermal intensity of a thermal profile of an area of a substrate under or over a lamp and the adjustable reflector, and in response to the thermal intensity being outside of desired parameters, adjusting the reflector profile of the reflector assembly along a centerline path.

公开(公告)号：US20240248282A1

公开(公告)日：2024-07-25

申请号：US18159214

申请日：2023-01-25

Applicant: Applied Materials, Inc.

Inventor： Ala MORADIAN ,  Saurabh CHOPRA ,  Lori D. WASHINGTON

IPC: G02B7/28 ,  G01J5/10 ,  G02B26/02 ,  H01L21/67

CPC classification number: G02B7/28 ,  G01J5/10 ,  G02B26/02 ,  H01L21/67115 ,  G02B26/004

Abstract: Embodiments herein are generally directed to electronic device manufacturing and, more particularly, to systems and methods for lamp heating in thermal processing chambers. In one embodiment, a substrate processing chamber includes a lid, a floor, and a processing volume between the lid and the floor. An upper window is disposed between the lid and the processing volume, a lower window is disposed between the floor and the processing volume. A lamp head is disposed between the lower window and the floor or between the upper window and the lid. At least one lamp is disposed within the lamp head, and a lens is disposed between the lamp head and the processing volume. In another embodiment, a plurality of lamps is disposed within the lamp head including at least one first lamp operating at a first wavelength and at least one second lamp operating at a second wavelength.

公开(公告)号：US20240088222A1

公开(公告)日：2024-03-14

申请号：US17943137

申请日：2022-09-12

Applicant: Applied Materials, Inc.

Inventor： Shawn THOMAS ,  Saurabh CHOPRA ,  John TOLLE

IPC: H01L29/08 ,  C23C16/22 ,  C23C16/56 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/0847 ,  C23C16/22 ,  C23C16/56 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02592 ,  H01L21/02598 ,  H01L21/02661 ,  H01L21/02672 ,  H01L21/02675 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78696

Abstract: A processing system includes one or more processing chambers, and a system controller configured to cause the processing system to perform (a) a pre-clean process on exposed surfaces of a semiconductor structure, the semiconductor structure comprising a first semiconductor region, a second semiconductor region separated from the first semiconductor region by a trench, and a dielectric layer over at least a portion of the first semiconductor region and the second semiconductor region, (b) a first deposition process to form an amorphous silicon-containing layer on the exposed surfaces of the semiconductor structure, (c) a recrystallization anneal process to recrystallize at least a portion of the amorphous silicon-containing layer to form a silicon-containing crystalline layer within the trench, (d) an etch process to remove remaining portions of the amorphous silicon-containing layer, and (e) a second deposition process, to epitaxially form a source/drain region over the silicon-containing crystalline layer within the trench.

公开(公告)号：US20230037320A1

公开(公告)日：2023-02-09

申请号：US17396371

申请日：2021-08-06

Applicant: Applied Materials, Inc.

Inventor： Chen-Ying WU ,  Zhiyuan YE ,  Xuebin LI ,  Sathya CHARY ,  Yi-Chiau HUANG ,  Saurabh CHOPRA

IPC: H01L21/02 ,  H01L29/423 ,  H01L29/08 ,  H01L29/66

Abstract: Embodiments described herein relate to a method of epitaxial deposition of p-channel metal oxide semiconductor (MMOS) source/drain regions within horizontal gate all around (hGAA) device structures. Combinations of precursors are described herein, which grow of the source/drain regions on predominantly surfaces with reduced or negligible growth on surfaces. Therefore, growth of the source/drain regions is predominantly located on the top surface of a substrate instead of the alternating layers of the hGAA structure. The precursor combinations include a silicon containing precursor, a germanium containing precursor, and a boron containing precursor. At least one of the precursors further includes chlorine.

公开(公告)号：US20220310390A1

公开(公告)日：2022-09-29

申请号：US17616131

申请日：2020-06-10

Applicant: Applied Materials, Inc.

Inventor： Yi-Chiau HUANG ,  Chen-Ying WU ,  Abhishek DUBE ,  Chia Cheng CHIN ,  Saurabh CHOPRA

IPC: H01L21/02 ,  H01L29/08 ,  H01L21/8234 ,  C30B25/18 ,  C30B29/52 ,  C23C16/06

Abstract: One or more embodiments described herein relate to selective methods for fabricating devices and structures. In these embodiments, the devices are exposed inside the process volume of a process chamber. Precursor gases are flowed in the process volume at certain flow ratios and at certain process conditions. The process conditions described herein result in selective epitaxial layer growth on the {100} planes of the crystal planes of the devices, which corresponds to the top of each of the fins. Additionally, the process conditions result in selective etching of the {110} plane of the crystal planes, which corresponds to the sidewalls of each of the fins. As such, the methods described herein provide a way to grow or etch epitaxial films at different crystal planes. Furthermore, the methods described herein allow for simultaneous epitaxial film growth and etch to occur on the different crystal planes.

公开(公告)号：US20190382917A1

公开(公告)日：2019-12-19

申请号：US16550933

申请日：2019-08-26

Applicant: Applied Materials, Inc.

Inventor： Christopher S. OLSEN ,  Theresa K. GUARINI ,  Jeffrey TOBIN ,  Lara HAWRYLCHAK ,  Peter STONE ,  Chi Wei LO ,  Saurabh CHOPRA

IPC: C30B25/18 ,  C30B29/08 ,  C30B29/06

Abstract: Embodiments of the present invention generally relate to methods for removing contaminants and native oxides from substrate surfaces. The methods generally include removing contaminants disposed on the substrate surface using a plasma process, and then cleaning the substrate surface by use of a remote plasma assisted dry etch process.

公开(公告)号：US20240347602A1

公开(公告)日：2024-10-17

申请号：US18632003

申请日：2024-04-10

Applicant: Applied Materials, Inc.

Inventor： Fredrick FISHBURN ,  Balasubramanian PRANATHARTHIHARAN ,  Abhishek DUBE ,  Saurabh CHOPRA

IPC: H01L29/165 ,  H01L21/02 ,  H01L21/306 ,  H01L29/04 ,  H10B12/00

CPC classification number: H01L29/165 ,  H01L21/02532 ,  H01L21/30604 ,  H01L29/045 ,  H10B12/00

Abstract: A three-dimensional semiconductor (3D) device. The 3D device may include a substrate, and a monocrystalline layer stack. The monocrystalline layer stack may include at least one monocrystalline semiconductor layer, separated from, and disposed over a main surface of the substrate. The 3D device may further include a plurality of epitaxial heterostructures, integrally grown from the at least one monocrystalline semiconductor layer. As such, a first epitaxial heterostructure may be disposed on a lower surface of the at least one monocrystalline semiconductor layer, facing the substrate, and wherein a second epitaxial heterostructure may be disposed on an upper surface of the monocrystalline semiconductor layer, opposite the lower surface.