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    METHOD OF SIMULTANEOUS SILICIDATION ON SOURCE AND DRAIN OF NMOS AND PMOS TRANSISTORS
    1.
    发明申请
    METHOD OF SIMULTANEOUS SILICIDATION ON SOURCE AND DRAIN OF NMOS AND PMOS TRANSISTORS 有权

    公开(公告)号：US20220139784A1

    公开(公告)日：2022-05-05

    申请号：US17085850

    申请日：2020-10-30

    Applicant: Applied Materials, Inc.

    Inventor： Xuebin LI

    IPC: H01L21/8238 ,  H01J37/32 ,  C23C16/50 ,  C23C16/42 ,  C23C16/52

    Abstract: A method and apparatus for the formation of a metal-oxide semiconductor FET (MOSFET) device is disclosed herein. The method of formation includes the utilization of a silicon-germanium seed layer deposited over an n-channel metal-oxide semiconductor (NMOS) device and a p-channel metal-oxide semiconductor (PMOS) device. The seed layer may be one seed layer deposited over both the NMOS source/drain regions and the PMOS source/drain regions or two doped seed layers wherein a first doped seed layer is deposited over the PMOS source/drain regions and a second doped seed layer is deposited over the NMOS source/drain regions. The seed layer enables simultaneous formation of a silicide over both the PMOS source/drain regions and the NMOS source/drain regions. The silicide formation consumes the seed layer and forms a silicide layer which varies in composition depending upon the composition of the absorbed seed layer.

    CARBON ADDITION FOR LOW RESISTIVITY IN SITU DOPED SILICON EPITAXY
    2.
    发明申请
    CARBON ADDITION FOR LOW RESISTIVITY IN SITU DOPED SILICON EPITAXY 审中-公开
    用于低电阻率的碳添加剂在原位硅胶外延中

    公开(公告)号：US20150221730A1

    公开(公告)日：2015-08-06

    申请号：US14688512

    申请日：2015-04-16

    Applicant: APPLIED MATERIALS, INC.

    Inventor： Zhiyuan YE ,  Xuebin LI ,  Saurabh CHOPRA ,  Yihwan KIM

    IPC: H01L29/36 ,  H01L29/167

    CPC classification number: H01L29/36 ,  H01L21/0245 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/02664 ,  H01L21/823814 ,  H01L29/167 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

    Abstract: Embodiments of the present invention generally relate to methods of forming epitaxial layers and devices having epitaxial layers. The methods generally include forming a first epitaxial layer including phosphorus and carbon on a substrate, and then forming a second epitaxial layer including phosphorus and carbon on the first epitaxial layer. The second epitaxial layer has a lower phosphorus concentration than the first epitaxial layer, which allows for selective etching of the second epitaxial layer and undesired amorphous silicon or polysilicon deposited during the depositions. The substrate is then exposed to an etchant to remove the second epitaxial layer and undesired amorphous silicon or polysilicon. The carbon present in the first and second epitaxial layers reduces phosphorus diffusion, which allows for higher phosphorus doping concentrations. The increased phosphorus concentrations reduce the resistivity of the final device. The devices include epitaxial layers having a resistivity of less than about 0.381 milliohm-centimeters.

    Abstract translation: 本发明的实施例一般涉及形成外延层的方法和具有外延层的器件。 所述方法通常包括在衬底上形成包括磷和碳的第一外延层，然后在第一外延层上形成包括磷和碳的第二外延层。 第二外延层具有比第一外延层更低的磷浓度，其允许在沉积期间沉积的第二外延层和不期望的非晶硅或多晶硅的选择性蚀刻。 然后将衬底暴露于蚀刻剂以除去第二外延层和不期望的非晶硅或多晶硅。 存在于第一和第二外延层中的碳减少磷扩散，这允许更高的磷掺杂浓度。 增加的磷浓度降低了最终装置的电阻率。 这些器件包括具有小于约0.381毫欧姆厘米的电阻率的外延层。

    METHOD OF SIMULTANEOUS SILICIDATION ON SOURCE AND DRAIN OF NMOS AND PMOS TRANSISTORS
    3.
    发明申请
    METHOD OF SIMULTANEOUS SILICIDATION ON SOURCE AND DRAIN OF NMOS AND PMOS TRANSISTORS 有权

    公开(公告)号：US20240387290A1

    公开(公告)日：2024-11-21

    申请号：US18786887

    申请日：2024-07-29

    Applicant: Applied Materials, Inc.

    Inventor： Xuebin LI

    IPC: H01L21/8238 ,  C23C16/42 ,  C23C16/50 ,  C23C16/52 ,  H01J37/32 ,  H01L21/285

    Abstract: A method and apparatus for the formation of a metal-oxide semiconductor FET (MOSFET) device is disclosed herein. The method of formation includes the utilization of a silicon-germanium seed layer deposited over an n-channel metal-oxide semiconductor (NMOS) device and a p-channel metal-oxide semiconductor (PMOS) device. The seed layer may be one seed layer deposited over both the NMOS source/drain regions and the PMOS source/drain regions or two doped seed layers wherein a first doped seed layer is deposited over the PMOS source/drain regions and a second doped seed layer is deposited over the NMOS source/drain regions. The seed layer enables simultaneous formation of a silicide over both the PMOS source/drain regions and the NMOS source/drain regions. The silicide formation consumes the seed layer and forms a silicide layer which varies in composition depending upon the composition of the absorbed seed layer.

    ANISOTROPIC SIGE:B EPITAXIAL FILM GROWTH FOR GATE ALL AROUND TRANSISTOR
    5.
    发明申请
    ANISOTROPIC SIGE:B EPITAXIAL FILM GROWTH FOR GATE ALL AROUND TRANSISTOR 有权

    公开(公告)号：US20230037320A1

    公开(公告)日：2023-02-09

    申请号：US17396371

    申请日：2021-08-06

    Applicant: Applied Materials, Inc.

    Inventor： Chen-Ying WU ,  Zhiyuan YE ,  Xuebin LI ,  Sathya CHARY ,  Yi-Chiau HUANG ,  Saurabh CHOPRA

    IPC: H01L21/02 ,  H01L29/423 ,  H01L29/08 ,  H01L29/66

    Abstract: Embodiments described herein relate to a method of epitaxial deposition of p-channel metal oxide semiconductor (MMOS) source/drain regions within horizontal gate all around (hGAA) device structures. Combinations of precursors are described herein, which grow of the source/drain regions on predominantly surfaces with reduced or negligible growth on surfaces. Therefore, growth of the source/drain regions is predominantly located on the top surface of a substrate instead of the alternating layers of the hGAA structure. The precursor combinations include a silicon containing precursor, a germanium containing precursor, and a boron containing precursor. At least one of the precursors further includes chlorine.

    METHOD TO GROW THIN EPITAXIAL FILMS AT LOW TEMPERATURE
    9.
    发明申请
    METHOD TO GROW THIN EPITAXIAL FILMS AT LOW TEMPERATURE 有权
    在低温下生长薄膜的方法

    公开(公告)号：US20160126093A1

    公开(公告)日：2016-05-05

    申请号：US14870792

    申请日：2015-09-30

    Applicant: Applied Materials, Inc.

    Inventor： Abhishek DUBE ,  Hua CHUNG ,  Jenn-Yue WANG ,  Xuebin LI ,  Yi-Chiau HUANG ,  Schubert S. CHU

    IPC: H01L21/02 ,  H01L29/78

    CPC classification number: H01L21/823431 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/02516 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/3065 ,  H01L29/7848 ,  H01L29/7851

    Abstract: Implementations of the present disclosure generally relate to methods for epitaxial growth of a silicon material on an epitaxial film. In one implementation, the method includes forming an epitaxial film over a semiconductor fin, wherein the epitaxial film includes a top surface having a first facet and a second facet, and forming an epitaxial layer on at least the top surface of the epitaxial film by alternatingly exposing the top surface to a first precursor gas comprising one or more silanes and a second precursor gas comprising one or more chlorinated silanes at a temperature of about 375° C. to about 450° C. and a chamber pressure of about 5 Torr to about 20 Torr.

    Abstract translation: 本公开的实施方式一般涉及在外延膜上硅材料外延生长的方法。 在一个实施方案中，该方法包括在半导体鳍片上形成外延膜，其中外延膜包括具有第一面和第二面的顶表面，并且通过交替地在至少外延膜的顶表面上形成外延层 将顶表面暴露于包含一种或多种硅烷的第一前体气体和包含一种或多种氯化硅烷的第二前体气体，其温度为约375℃至约450℃，室压力为约5托至约 20乇

    METHODS OF EPITAXIALLY GROWING BORON-CONTAINING STRUCTURES
    10.
    发明公开
    METHODS OF EPITAXIALLY GROWING BORON-CONTAINING STRUCTURES 审中-公开

    公开(公告)号：US20230223257A1

    公开(公告)日：2023-07-13

    申请号：US17573748

    申请日：2022-01-12

    Applicant: Applied Materials, Inc.

    Inventor： Xuebin LI ,  Sathya CHARY ,  Joe MARGETIS

    IPC: H01L21/02 ,  C30B25/18 ,  C30B29/10 ,  C23C16/02 ,  C23C16/38

    CPC classification number: H01L21/02579 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  C30B25/186 ,  C30B29/10 ,  C23C16/0236 ,  C23C16/38

    Abstract: Embodiments of the present invention generally relate to methods of epitaxially growing boron-containing structures. In an embodiment, a method of depositing a structure comprising boron and a Group IV element on a substrate is provided. The method includes heating the substrate at a temperature of about 300° C. or more within a chamber, the substrate having a dielectric material and a single crystal formed thereon. The method further includes flowing a first process gas and a second process gas into the chamber, wherein: the first process gas comprises at least one boron-containing gas comprising a haloborane; and the second process gas comprises at least one Group IV element-containing gas. The method further includes exposing the substrate to the first and second process gases to epitaxially and selectively deposit the structure comprising boron and the Group IV element on the single crystal.

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