公开(公告)号：US20130084816A1

公开(公告)日：2013-04-04

申请号：US13249741

申请日：2011-09-30

Applicant: Ray (Ramon) Gomez ,  Leonard Dauphinee ,  Massimo Brandolini ,  Jianhong Xiao ,  Dongsoo Koh ,  Young Shin ,  Chonghua Zhong ,  Rezaur Rahman Khan

Inventor： Ray (Ramon) Gomez ,  Leonard Dauphinee ,  Massimo Brandolini ,  Jianhong Xiao ,  Dongsoo Koh ,  Young Shin ,  Chonghua Zhong ,  Rezaur Rahman Khan

IPC: H04W88/02

CPC classification number: H04B1/0475 ,  H03M1/66

Abstract: Embodiments provide transmitter topologies that improve the power efficiency and bandwidth of RF transmitters for high transmission power applications. In an embodiment, the common-emitter/source PA of conventional topologies is replaced with a current-input common-base/gate PA, which is stacked on top on an open-collector/drain current-output transmitter. The common-base/gate PA protects the output of the transmitter from large output voltage swings. The low input impedance of the common-base/gate PA makes the PA less susceptible to frequency roll-off, even in the presence of large parasitic capacitance produced by the transmitter. At the same time, the low input impedance of the common-base/gate PA reduces the voltage swing at the transmitter output and prevents the transmitter output from being compressed or modulated. In an embodiment, the DC output current of the transmitter is reused to bias the PA, which results in power savings compared to conventional transmitter topologies.

Abstract translation: 实施例提供了发射机拓扑，其提高用于高传输功率应用的RF发射机的功率效率和带宽。 在一个实施例中，常规拓扑的共发射极/源极PA被置于集电极/漏极电流输出发射器顶部堆叠的电流输入公共基极/栅极PA替代。 公共端/门PA保护发射机的输出免受大的输出电压摆幅。 公共基极/门极PA的低输入阻抗使得即使在发射机产生大的寄生电容的情况下，PA也不易于频率滚降。 同时，公共基极/门极PA的低输入阻抗降低了发射机输出端的电压摆幅，并防止发射机输出被压缩或调制。 在一个实施例中，与常规发射机拓扑相比，发射机的DC输出电流被重新用于偏置PA，这导致功率节省。

公开(公告)号：US08138608B2

公开(公告)日：2012-03-20

申请号：US12691255

申请日：2010-01-21

Applicant: Chonghua Zhong

Inventor： Chonghua Zhong

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L23/5382 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0293 ,  H05K3/321 ,  H05K3/3452 ,  H05K2201/0305 ,  H05K2201/09381 ,  H05K2201/09809 ,  H05K2201/0989 ,  H05K2201/10674 ,  H05K2203/173 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Methods, systems, and apparatuses for integrated circuit package substrates, integrated circuit packages, and processes for assembling the same, are provided. A substrate for a flip chip integrated circuit package includes a substrate body having opposing first and second surfaces. A solder mask layer covers at least a portion of the first surface of the substrate body. First and second electrically conductive features are formed on the substrate body. The first electrically conductive feature is a portion of a first electrical signal net, and the second electrically conductive feature is a portion of a second electrical signal net. The first and second electrically conductive features are configured to be selectively electrically coupled together by application of an electrically conductive material. The electrically conductive material may be a conductive epoxy, a jumper, a solder paste, a solder ball, or a solder bump that couples a flip chip die to the substrate.

Abstract translation: 提供了用于集成电路封装基板，集成电路封装以及用于组装其的工艺的方法，系统和装置。 用于倒装芯片集成电路封装的衬底包括具有相对的第一和第二表面的衬底本体。 焊接掩模层覆盖基板主体的第一表面的至少一部分。 第一和第二导电特征形成在衬底主体上。 第一导电特征是第一电信号网的一部分，第二导电特征是第二电信号网的一部分。 第一和第二导电特征被配置为通过施加导电材料选择性地电耦合在一起。 导电材料可以是导电环氧树脂，跳线，焊膏，焊球或将倒装芯片裸片耦合到衬底的焊料凸块。

公开(公告)号：US09153530B2

公开(公告)日：2015-10-06

申请号：US13162064

申请日：2011-06-16

Applicant: Chonghua Zhong ,  Kunzhong Hu

Inventor： Chonghua Zhong ,  Kunzhong Hu

IPC: H01L23/12 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/4846 ,  H01L23/49816 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2924/15311

Abstract: Systems and methods according to embodiments of the invention enable flip chip packaging using high density routing while minimizing the thickness and layer count of the flip chip package. By using a photoresist layer to create very fine traces on a metallic base layer, embodiments of the present invention combine advantages of leadframe substrates and laminate substrates by supporting high-density routing while minimizing layer count and manufacturing cost. Additionally, the use of raised metallic pads in a routing layer enables embodiments of the present invention to include highly compact traces that pass over IC die bond pad connection sites without directly coupling to these bond IC die bond pad connection sites. Further, embodiments of the present invention can support multiple thin routing layers without the need for organic (e.g., laminate) material separating these routing layers.

Abstract translation: 根据本发明的实施例的系统和方法使得能够使倒装芯片封装的厚度和层数最小化的高密度布线的倒装芯片封装。 通过使用光致抗蚀剂层在金属基底层上产生非常精细的迹线，本发明的实施例通过支持高密度布线同时最小化层数和制造成本来结合引线框架基板和层叠基板的优点。 此外，在布线层中使用凸起的金属焊盘使得本发明的实施例能够包括通过IC管芯接合焊盘连接位置的非常紧凑的迹线，而不直接耦合到这些接合IC管芯接合焊盘连接位置。 此外，本发明的实施例可以支持多个薄路由层，而不需要分离这些路由层的有机（例如，层叠）材料。

公开(公告)号：US20130134596A1

公开(公告)日：2013-05-30

申请号：US13306787

申请日：2011-11-29

Applicant: Kevin (Kunzhong) Hu ,  Chonghua Zhong ,  Edward Law

Inventor： Kevin (Kunzhong) Hu ,  Chonghua Zhong ,  Edward Law

IPC: H01L21/768 ,  H01L23/485

CPC classification number: H01L24/13 ,  H01L21/561 ,  H01L21/76801 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/19 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05073 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05672 ,  H01L2224/05684 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2224/03 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/013 ,  H01L2224/05552 ,  H01L2924/00

Abstract: There are disclosed herein various implementations of improved wafer level semiconductor packages. One exemplary implementation comprises forming a post-fabrication redistribution layer (post-Fab RDL) between first and second dielectric layers affixed over a surface of a wafer, and forming a window for receiving an electrical contact body in the second dielectric layer, the window exposing the post-Fab RDL. At least one of the first and second dielectric layers is a pre-formed dielectric layer, which may be affixed over the surface of the wafer using a lamination process. In one implementation, the window is formed using a direct laser ablation process.

Abstract translation: 这里公开了改进的晶片级半导体封装的各种实现方式。 一个示例性实现包括在固定在晶片表面上的第一和第二电介质层之间形成后制造再分配层（后Fab RDL），并形成用于接收第二介电层中的电接触体的窗口，窗口暴露 后Fab RDL。 第一和第二电介质层中的至少一个是预先形成的电介质层，其可以使用层压工艺固定在晶片的表面上。 在一个实施方案中，窗口使用直接激光烧蚀工艺形成。

公开(公告)号：US20100117245A1

公开(公告)日：2010-05-13

申请号：US12691255

申请日：2010-01-21

Applicant: Chonghua Zhong

Inventor： Chonghua Zhong

IPC: H01L23/488 ,  H05K1/11

CPC classification number: H01L23/5382 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0293 ,  H05K3/321 ,  H05K3/3452 ,  H05K2201/0305 ,  H05K2201/09381 ,  H05K2201/09809 ,  H05K2201/0989 ,  H05K2201/10674 ,  H05K2203/173 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Methods, systems, and apparatuses for integrated circuit package substrates, integrated circuit packages, and processes for assembling the same, are provided. A substrate for a flip chip integrated circuit package includes a substrate body having opposing first and second surfaces. A solder mask layer covers at least a portion of the first surface of the substrate body. First and second electrically conductive features are formed on the substrate body. The first electrically conductive feature is a portion of a first electrical signal net, and the second electrically conductive feature is a portion of a second electrical signal net. The first and second electrically conductive features are configured to be selectively electrically coupled together by application of an electrically conductive material. The electrically conductive material may be a conductive epoxy, a jumper, a solder paste, a solder ball, or a solder bump that couples a flip chip die to the substrate.

Abstract translation: 提供了用于集成电路封装基板，集成电路封装以及用于组装其的工艺的方法，系统和装置。 用于倒装芯片集成电路封装的衬底包括具有相对的第一和第二表面的衬底本体。 焊接掩模层覆盖基板主体的第一表面的至少一部分。 第一和第二导电特征形成在衬底主体上。 第一导电特征是第一电信号网的一部分，第二导电特征是第二电信号网的一部分。 第一和第二导电特征被配置为通过施加导电材料选择性地电耦合在一起。 导电材料可以是导电环氧树脂，跳线，焊膏，焊球或将倒装芯片裸片耦合到衬底的焊料凸块。

公开(公告)号：US20090051010A1

公开(公告)日：2009-02-26

申请号：US12073450

申请日：2008-03-05

Applicant: Sam Ziqun Zhao ,  Chonghua Zhong ,  Rezaur Rahman Khan

Inventor： Sam Ziqun Zhao ,  Chonghua Zhong ,  Rezaur Rahman Khan

IPC: H01L23/58 ,  H01L21/50

CPC classification number: H01L21/78 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H05K3/0052 ,  H05K2201/09063 ,  H05K2201/09681 ,  H05K2201/09781 ,  H01L2924/00

Abstract: Systems and methods for preventing damage to a unit with preventive structures are presented. In an embodiment, a unit of a collection of units includes a functional area and a preventive structure configured to prevent cracks from propagating into the functional area.

Abstract translation: 介绍了防止结构损坏装置的系统和方法。 在一个实施例中，单元集合的单元包括功能区域和预防结构，其被配置为防止裂纹传播到功能区域。