公开(公告)号：US5899736A

公开(公告)日：1999-05-04

申请号：US933955

申请日：1997-09-19

Applicant: Peter Weigand ,  Dirk Tobben

Inventor： Peter Weigand ,  Dirk Tobben

IPC: H01L27/04 ,  H01L21/82 ,  H01L21/822 ,  H01L23/525 ,  H01L29/00

CPC classification number: H01L23/5256 ,  H01L2924/0002

Abstract: A method for fabricating an electrically blowable fuse on a semiconductor substrate. The method includes forming a fuse portion 102 on the semiconductor substrate. The fuse portion is configured to turn substantially non-conductive when a current exceeding a predefined current level passes through the fuse portion. The method also includes depositing a substantially conformal first layer 302 of dielectric material above the fuse portion and depositing a second layer 304 of dielectric material above the first layer, thereby forming a protrusion of dielectric material above the fuse portion. The second layer being different from the first layer. The method further includes performing chemical-mechanical polish on the protrusion to form an opening through the second layer above the protrusion. There is also included etching, in a substantially isotropic manner, a portion of the first layer through the opening to form a microcavity 502 about the fuse portion. The etching is substantially selective to the second layer and the fuse portion. Additionally, there is included depositing a substantially conformal third layer 606 of dielectric material above the second layer, thereby closing the opening in the second layer.

Abstract translation: 一种在半导体衬底上制造可电熔熔断器的方法。 该方法包括在半导体衬底上形成熔丝部分102。 保险丝部分被配置为当超过预定电流水平的电流通过熔丝部分时基本上不导通。 该方法还包括在熔丝部分上沉积基本上保形的介电材料第一层302，并在第一层上方沉积介电材料的第二层304，由此在熔丝部分上方形成电介质材料的突起。 第二层与第一层不同。 该方法还包括在突起上执行化学机械抛光以形成通过突起上方的第二层的开口。 还包括以基本上各向同性的方式蚀刻通过开口的第一层的一部分，以围绕熔丝部分形成微腔502。 蚀刻对第二层和熔丝部分基本上是选择性的。 另外，包括在第二层上方沉积介电材料的基本上保形的第三层606，从而封闭第二层中的开口。

公开(公告)号：US06271142B1

公开(公告)日：2001-08-07

申请号：US09354743

申请日：1999-07-29

Applicant: Ulrike Gruening ,  Carl J. Radens ,  Dirk Tobben

Inventor： Ulrike Gruening ,  Carl J. Radens ,  Dirk Tobben

IPC: H01L21311

CPC classification number: H01L27/1087

Abstract: A process for manufacturing a deep trench capacitor in a trench. The capacitor comprises a collar in an upper region of the trench and a buried plate in a lower region of the trench. The improvement comprises, before forming the collar in the trench upper region, filling the trench lower region with a non-photosensitive underfill material such as spin-on-glass. The process may comprise the steps of (a) forming a deep trench in a substrate; (b) filling the trench lower region with an underfill material; (c) forming a collar in the trench upper region; (d) removing the underfill; and (e) forming a buried plate in the trench lower region.

Abstract translation: 一种在沟槽中制造深沟槽电容器的工艺。 电容器包括在沟槽的上部区域中的环形部分和在沟槽的下部区域中的掩埋板。 改进之处在于，在沟槽上部区域中形成套环之前，用非光敏底层填充材料（例如旋涂玻璃）填充沟槽下部区域。 该方法可以包括以下步骤：（a）在衬底中形成深沟槽; （b）用底部填充材料填充沟槽下部区域; （c）在所述沟槽上部区域中形成套环; （d）除去底部填充物; 和（e）在沟槽下部区域形成掩埋板。

公开(公告)号：US6066569A

公开(公告)日：2000-05-23

申请号：US940895

申请日：1997-09-30

Applicant: Dirk Tobben

Inventor： Dirk Tobben

IPC: H01L21/3205 ,  H01L21/311 ,  H01L21/312 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L21/302 ,  H01L21/461

CPC classification number: H01L21/31144 ,  H01L21/76813 ,  H01L2221/1021

Abstract: A process for the manufacture of silicon integrated circuits uses a dual damascene metallization process with an organic intermetal dielectric (14). A pattern to be etched is first etched in a hard mask (16) without exposing the underlying intermetal dielectric (14) and then transferred into the intermetal dielectric (14) on an enlarged scale.y

Abstract translation: 用于制造硅集成电路的方法使用具有有机金属间电介质的双镶嵌金属化工艺（14）。 要蚀刻的图案首先在硬掩模（16）中蚀刻，而不暴露下面的金属间电介质（14），然后以放大的尺度转移到金属间电介质（14）中。

公开(公告)号：US5977635A

公开(公告)日：1999-11-02

申请号：US939208

申请日：1997-09-29

Applicant: Dirk Tobben ,  Peter Weigand

Inventor： Dirk Tobben ,  Peter Weigand

IPC: H01L21/768 ,  H01L21/8242 ,  H01L23/522 ,  H01L23/532 ,  H01L27/10 ,  H01L27/108 ,  H01L23/48

CPC classification number: H01L23/5329 ,  H01L21/76831 ,  H01L21/76834 ,  H01L23/5222 ,  H01L2924/0002

Abstract: A method for forming a multi-level conductive structure on an integrated circuit. The method includes forming a first conductive layer 108 and forming a first dielectric layer 112 above the first conductive layer. The method further includes forming a second conductive layer 302 above the first dielectric layer. There is also included etching through the second conductive layer and at least partially into the first dielectric layer to form a trench 706 in the second conductive layer and the first dielectric layer, thereby removing at least a portion of the dielectric layer and forming a first conductive line 503 and a second conductive line 505 in the second conductive layer. Further, the method includes depositing a low capacitance material 908 into the trench. The low capacitance material represents a material having a dielectric constant lower than a dielectric constant of the first dielectric layer.

Abstract translation: 一种在集成电路上形成多层导电结构的方法。 该方法包括形成第一导电层108并在第一导电层上方形成第一介电层112。 该方法还包括在第一介电层上形成第二导电层302。 还包括蚀刻穿过第二导电层并且至少部分地进入第一介电层以在第二导电层和第一介电层中形成沟槽706，由此去除介电层的至少一部分并形成第一导电 线503和在第二导电层中的第二导线505。 此外，该方法包括将低电容材料908沉积到沟槽中。 低电容材料表示介电常数低于第一介电层的介电常数的材料。

公开(公告)号：US5926716A

公开(公告)日：1999-07-20

申请号：US829255

申请日：1997-03-31

Applicant: Dirk Tobben ,  Peter Weigand

Inventor： Dirk Tobben ,  Peter Weigand

IPC: H01L27/04 ,  B81B3/00 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/20

CPC classification number: B81C1/00111 ,  H01L27/10852 ,  H01L28/87 ,  H01L28/91 ,  B81C2201/0109 ,  B81C2201/0159 ,  H01L28/88 ,  H01L28/92

Abstract: A method for forming a microstructure includes photolithographically forming a vertically extending post on a portion of a surface of a substrate to provide a first structure. A flowable, sacrificial material is deposited over a surface of the first structure. The flowable, sacrificial materially flows off the top surface and sidewall portions of the post onto adjacent portions of the surface of the substrate to provide a second structure. A non-sacrificial material is deposited over a surface of the second structure. The non-sacrificial material is deposited to conform to the surface of the second structure. The non-sacrificial is deposited over the sacrificial material, over the sidewall portions and over the top surface of the post. The deposited sacrificial material is selectively removed while the non-sacrificial material remains to form a third structure with a horizontal member provided by the non-sacrificial material. The horizontal member is supported a predetermined distance above the surface of the substrate by a lower portion of the post. The flowable material is a flowable oxide, for example, hydrogensilsesquioxane glass, and the post has a width less than 20 .mu.m. The resulting structure, formed with a single photolithographic step, is used for supporting a capacitor deposited over it. The capacitor is formed as a sequence of deposition steps; i.e., depositing a first conductive layer over a surface of the support structure; depositing a dielectric layer over the conductive layer; and depositing a second conductive layer over the dielectric layer.

Abstract translation: 一种用于形成微结构的方法包括光刻地形成垂直延伸的柱体，以在衬底表面的一部分上提供第一结构。 可流动的牺牲材料沉积在第一结构的表面上。 可流动的牺牲物质地从柱的顶表面和侧壁部分流出到衬底的表面的相邻部分上以提供第二结构。 非牺牲材料沉积在第二结构的表面上。 沉积非牺牲材料以符合第二结构的表面。 非牺牲材料沉积在牺牲材料上，在侧壁部分上方并在柱的顶表面上方。 选择性地去除沉积的牺牲材料，同时非牺牲材料保留以形成具有由非牺牲材料提供的水平构件的第三结构。 水平构件通过柱的下部支撑在基板的表面上方预定距离。 可流动材料是可流动的氧化物，例如氢倍半硅氧烷玻璃，柱的宽度小于20μm。 用单个光刻步骤形成的所得结构用于支撑沉积在其上的电容器。 电容器形成为一系列沉积步骤; 即在支撑结构的表面上沉积第一导电层; 在导电层上沉积介电层; 以及在所述电介质层上沉积第二导电层。

公开(公告)号：US5854126A

公开(公告)日：1998-12-29

申请号：US829257

申请日：1997-03-31

Applicant: Dirk Tobben ,  Bruno Spuler ,  Martin Gutsche ,  Peter Weigand

Inventor： Dirk Tobben ,  Bruno Spuler ,  Martin Gutsche ,  Peter Weigand

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/12 ,  H05K1/00 ,  H05K3/06 ,  H05K3/22 ,  H05K3/24 ,  H01L21/469 ,  H01L21/312

CPC classification number: H05K3/061 ,  H01L21/32139 ,  H01L21/76838 ,  H05K1/0284 ,  H05K2201/09018 ,  H05K2203/0585

Abstract: A method for forming a plurality of electrically conductive wires on a substrate. The method includes forming a relatively non-planar metal layer over a surface of the substrate. A self-planarizing material is deposited over the metal layer. The self-planarizing material forms a planarization layer over the surface of the metal layer. The planarization layer has a surface relatively planar compared to the relatively non-planar metal layer. A photoresist layer is deposited over the surface of the planarization layer. The photoresist layer is patterned with a plurality of grooves to form a mask with such grooves exposing underling portions of the planarization layer. The photoresist mask is used as a mask to etch grooves in the exposed portions of the planarization layer and thereby form a second mask. The second mask exposes underling portions of the relatively non-planar metal layer. The second mask is used to etch grooves in the relatively non-planar conductive metal layer and thereby form the plurality of electrically conductive wires in the metal layer. The wires are separated from each other by the grooves formed in the relatively non-planar metal layer. The planarization layer is formed by a spinning-on an organic polymer, for example an organic polymer having silicon, or a flowable oxide, or a hydrogensilsequioxane, or divinyl-siloxane-benzocyclobutene. The metal layer is etched using reactive ion etching. The planarization layer is removed using a wet chemical etch.

Abstract translation: 一种在基板上形成多根导电线的方法。 该方法包括在衬底的表面上形成相对非平面的金属层。 自平面化材料沉积在金属层上。 自平面化材料在金属层的表面上形成平坦化层。 与相对非平面的金属层相比，平坦化层具有相对平坦的表面。 在平坦化层的表面上沉积光致抗蚀剂层。 用多个凹槽对光致抗蚀剂层进行图案化以形成掩模，该掩模具有暴露平坦化层的下部的这种凹槽。 光致抗蚀剂掩模用作掩模以蚀刻平坦化层的暴露部分中的凹槽，从而形成第二掩模。 第二掩模暴露相对非平面金属层的下层部分。 第二掩模用于蚀刻相对非平面导电金属层中的凹槽，从而在金属层中形成多个导电线。 电线通过在相对非平面的金属层中形成的凹槽彼此分离。 平坦化层是通过旋涂有机聚合物，例如具有硅的有机聚合物，或可流动的氧化物，或氢化二烷基锡，或二乙烯基 - 硅氧烷 - 苯并环丁烯等形成的。 使用反应离子蚀刻蚀刻金属层。 使用湿化学蚀刻去除平坦化层。

公开(公告)号：US20050020009A1

公开(公告)日：2005-01-27

申请号：US10480999

申请日：2002-06-13

Applicant: Dirk Tobben

Inventor： Dirk Tobben

IPC: H01L21/336 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10894 ,  H01L27/10897

Abstract: The invention relates to a method for producing a memory component comprising a memory location (104) having memory cells and first control electrode strips (162) for controlling the individual memory cells, and a peripheral area (106) having peripheral elements and second control electrode strips (164) for controlling said peripheral elements. The inventive method enables the expansion of the second control electrode strips (164) in the peripheral area (106) to be approximately randomly adjusted to minimum line widths, without influencing or changing the expansion of the first control electrode strips (162) in the memory location (104).

Abstract translation: 本发明涉及一种用于产生存储器组件的方法，该存储器组件包括具有存储单元的存储器位置（104）和用于控制各个存储单元的第一控制电极条（162），以及具有外围元件和第二控制电极 用于控制所述外围元件的条带（164）。 本发明的方法使得能够将周边区域（106）中的第二控制电极条（164）的扩展大致随机地调整为最小线宽，而不会影响或改变存储器中第一控制电极条（162）的扩展 位置（104）。

公开(公告)号：US06492282B1

公开(公告)日：2002-12-10

申请号：US08846925

申请日：1997-04-30

Applicant: Dirk Tobben ,  Peter Weigand ,  Matthias Ilg

Inventor： Dirk Tobben ,  Peter Weigand ,  Matthias Ilg

IPC: H01L21316

CPC classification number: H01L21/31051 ,  H01L21/76801 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76837

Abstract: A method of filling gaps between adjacent gate electrodes of a semiconductor structure. A self-planarizing material is deposited over the structure. A first portion of such material flow between the gate electrode to fill the gaps and a second portion of such material becomes deposited over tops of the gate electrodes and over the gaps to form a layer with a substantially planar surface. A phosphorous dopant is formed in the second portion of the self-planarizing material. Thus, relatively small gaps may be filled effectively with a layer having a very planar surface for subsequent photolithography. The phosphorous dopant provides gettering to remove adverse effects of alkali contaminant ions which may enter the gap filling material. The dielectric constant of the material filing the gaps, i.e., the first portion of the gap filling material, being substantially free of such contaminants, has a relatively low dielectric constant thereby reducing electrical coupling between adjacent electrodes. The self-planarizing material is a flowable material. The flowable oxide may be spun on or may be deposited by gaseous deposition. The phosphorous dopant may be provided by, for example: implanting phosphorous ions into the second portion of the self-planarizing layer and heating the material to both cure such material and activate the phosphorous ions; depositing a phosphorous doped layer over the layer of self-planarizing material, heating the structure to out-diffuse the phosphorous dopant into the second portion of the self-planarizing material and selectively removing the deposited layer; or by curing the spun-on self-planarizing material in a phosphine environment.

Abstract translation: 一种在半导体结构的相邻栅电极之间填充间隙的方法。 在该结构上沉积自平面化材料。 这种材料的第一部分在栅极电极之间流动以填充间隙，并且这种材料的第二部分沉积在栅电极的顶部上并在间隙上沉积以形成具有基本平坦表面的层。 在自平面化材料的第二部分中形成磷掺杂剂。 因此，可以用具有非常平坦的表面的层有效地填充相对小的间隙用于随后的光刻。 磷掺杂剂提供吸气以除去可能进入间隙填充材料的碱性污染物离子的不利影响。 填充间隙的材料的介电常数，即间隙填充材料的第一部分基本上没有这种污染物，具有相对低的介电常数，从而减少相邻电极之间的电耦合。 自平面化材料是可流动的材料。 可流动的氧化物可以通过气相沉积或在其上沉积。 磷掺杂剂可以通过例如：将磷离子注入到自平坦化层的第二部分中并加热材料以固化这种材料并激活磷离子来提供磷掺杂剂; 在所述自平面化材料层上沉积磷掺杂层，加热所述结构以将所述磷掺杂剂扩散到所述自平面化材料的第二部分中并选择性地去除所述沉积层; 或通过在磷化氢环境中固化纺丝自平面化材料。

公开(公告)号：US06426254B2

公开(公告)日：2002-07-30

申请号：US09328763

申请日：1999-06-09

Applicant: Stephen Kudelka ,  Alexander Michaelis ,  Dirk Tobben

Inventor： Stephen Kudelka ,  Alexander Michaelis ,  Dirk Tobben

IPC: H01L218242

CPC classification number: H01L27/10861 ,  H01L21/30608

Abstract: In accordance with the present invention, a method for expanding trenches includes the steps of forming a trench in a substrate, preparing surfaces withIn the trench by etching the surfaces with a wet etchant to provide a hydrogen terminated silicon surface and anisoropically wet etching the trench to expand the trench.

Abstract translation: 根据本发明，用于扩展沟槽的方法包括以下步骤：在衬底中形成沟槽，通过用湿蚀刻剂蚀刻表面来在沟槽中制备表面，以提供氢封端的硅表面，并将各向异性湿法蚀刻沟槽 扩大沟渠。

公开(公告)号：US06404000B1

公开(公告)日：2002-06-11

申请号：US09599261

申请日：2000-06-22

Applicant: Rama Divakaruni ,  Rajarao Jammy ,  Byeong Y. Kim ,  Jack A. Mandelman ,  Akira Sudo ,  Dirk Tobben

Inventor： Rama Divakaruni ,  Rajarao Jammy ,  Byeong Y. Kim ,  Jack A. Mandelman ,  Akira Sudo ,  Dirk Tobben

IPC: H01L2972

CPC classification number: H01L27/10861 ,  H01L27/10867 ,  H01L29/945

Abstract: A memory structure having a trenched formed in a substrate. A collar oxide is located in an upper portion of the trench and includes a pedestal portion. A method of forming a memory device having a collar oxide with pedestal collar is also disclosed.

Abstract translation: 一种在衬底中形成有沟槽的存储器结构。 环状氧化物位于沟槽的上部，并且包括基座部分。 还公开了一种形成具有带衬垫环的环形氧化物的存储器件的方法。