公开(公告)号：US09758291B2

公开(公告)日：2017-09-12

申请号：US13512374

申请日：2010-11-18

Applicant: Peter Weigand ,  Gunter Quass ,  Jens von Waaden

Inventor： Peter Weigand ,  Gunter Quass ,  Jens von Waaden

IPC: B65D90/48 ,  B65D81/38

CPC classification number: B65D81/38 ,  B65D90/48

Abstract: A port arrangement is configured for accessing a demountable component in an interior of an apparatus or container. The port arrangement includes an inner port having a port tube and forming a releasable connection with an internal component. The port tube of the inner port is guided through an outer port that is to an outer jacket.

公开(公告)号：US6136709A

公开(公告)日：2000-10-24

申请号：US413265

申请日：1999-10-06

Applicant: Sven Schmidbauer ,  Stefan J. Weber ,  Peter Weigand ,  Larry Clevenger ,  Roy Iggulden

Inventor： Sven Schmidbauer ,  Stefan J. Weber ,  Peter Weigand ,  Larry Clevenger ,  Roy Iggulden

IPC: H01L21/768 ,  H01L21/24 ,  H01L21/4763

CPC classification number: H01L21/76877

Abstract: A method for depositing metal lines for semiconductor devices, in accordance with the present invention includes the steps of providing a semiconductor wafer including a dielectric layer formed on the wafer, the dielectric layer having vias formed therein and placing the wafer in a deposition chamber. The method further includes depositing a metal on the wafer to fill the vias wherein the metal depositing is initiated when the wafer is at a first temperature and the depositing is continued while heating the wafer to a target temperature which is greater than the first temperature.

Abstract translation: 根据本发明的用于沉积半导体器件的金属线的方法包括以下步骤：提供包括在晶片上形成的电介质层的半导体晶片，所述电介质层具有形成在其中的通孔并将晶片放置在沉积室中。 该方法还包括在晶片上沉积金属以填充通孔，其中当晶片处于第一温度时开始金属沉积，并且在将晶片加热到大于第一温度的目标温度的同时继续沉积。

公开(公告)号：US5977635A

公开(公告)日：1999-11-02

申请号：US939208

申请日：1997-09-29

Applicant: Dirk Tobben ,  Peter Weigand

Inventor： Dirk Tobben ,  Peter Weigand

IPC: H01L21/768 ,  H01L21/8242 ,  H01L23/522 ,  H01L23/532 ,  H01L27/10 ,  H01L27/108 ,  H01L23/48

CPC classification number: H01L23/5329 ,  H01L21/76831 ,  H01L21/76834 ,  H01L23/5222 ,  H01L2924/0002

Abstract: A method for forming a multi-level conductive structure on an integrated circuit. The method includes forming a first conductive layer 108 and forming a first dielectric layer 112 above the first conductive layer. The method further includes forming a second conductive layer 302 above the first dielectric layer. There is also included etching through the second conductive layer and at least partially into the first dielectric layer to form a trench 706 in the second conductive layer and the first dielectric layer, thereby removing at least a portion of the dielectric layer and forming a first conductive line 503 and a second conductive line 505 in the second conductive layer. Further, the method includes depositing a low capacitance material 908 into the trench. The low capacitance material represents a material having a dielectric constant lower than a dielectric constant of the first dielectric layer.

Abstract translation: 一种在集成电路上形成多层导电结构的方法。 该方法包括形成第一导电层108并在第一导电层上方形成第一介电层112。 该方法还包括在第一介电层上形成第二导电层302。 还包括蚀刻穿过第二导电层并且至少部分地进入第一介电层以在第二导电层和第一介电层中形成沟槽706，由此去除介电层的至少一部分并形成第一导电 线503和在第二导电层中的第二导线505。 此外，该方法包括将低电容材料908沉积到沟槽中。 低电容材料表示介电常数低于第一介电层的介电常数的材料。

公开(公告)号：US5926716A

公开(公告)日：1999-07-20

申请号：US829255

申请日：1997-03-31

Applicant: Dirk Tobben ,  Peter Weigand

Inventor： Dirk Tobben ,  Peter Weigand

IPC: H01L27/04 ,  B81B3/00 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/20

CPC classification number: B81C1/00111 ,  H01L27/10852 ,  H01L28/87 ,  H01L28/91 ,  B81C2201/0109 ,  B81C2201/0159 ,  H01L28/88 ,  H01L28/92

Abstract: A method for forming a microstructure includes photolithographically forming a vertically extending post on a portion of a surface of a substrate to provide a first structure. A flowable, sacrificial material is deposited over a surface of the first structure. The flowable, sacrificial materially flows off the top surface and sidewall portions of the post onto adjacent portions of the surface of the substrate to provide a second structure. A non-sacrificial material is deposited over a surface of the second structure. The non-sacrificial material is deposited to conform to the surface of the second structure. The non-sacrificial is deposited over the sacrificial material, over the sidewall portions and over the top surface of the post. The deposited sacrificial material is selectively removed while the non-sacrificial material remains to form a third structure with a horizontal member provided by the non-sacrificial material. The horizontal member is supported a predetermined distance above the surface of the substrate by a lower portion of the post. The flowable material is a flowable oxide, for example, hydrogensilsesquioxane glass, and the post has a width less than 20 .mu.m. The resulting structure, formed with a single photolithographic step, is used for supporting a capacitor deposited over it. The capacitor is formed as a sequence of deposition steps; i.e., depositing a first conductive layer over a surface of the support structure; depositing a dielectric layer over the conductive layer; and depositing a second conductive layer over the dielectric layer.

Abstract translation: 一种用于形成微结构的方法包括光刻地形成垂直延伸的柱体，以在衬底表面的一部分上提供第一结构。 可流动的牺牲材料沉积在第一结构的表面上。 可流动的牺牲物质地从柱的顶表面和侧壁部分流出到衬底的表面的相邻部分上以提供第二结构。 非牺牲材料沉积在第二结构的表面上。 沉积非牺牲材料以符合第二结构的表面。 非牺牲材料沉积在牺牲材料上，在侧壁部分上方并在柱的顶表面上方。 选择性地去除沉积的牺牲材料，同时非牺牲材料保留以形成具有由非牺牲材料提供的水平构件的第三结构。 水平构件通过柱的下部支撑在基板的表面上方预定距离。 可流动材料是可流动的氧化物，例如氢倍半硅氧烷玻璃，柱的宽度小于20μm。 用单个光刻步骤形成的所得结构用于支撑沉积在其上的电容器。 电容器形成为一系列沉积步骤; 即在支撑结构的表面上沉积第一导电层; 在导电层上沉积介电层; 以及在所述电介质层上沉积第二导电层。

公开(公告)号：US5854126A

公开(公告)日：1998-12-29

申请号：US829257

申请日：1997-03-31

Applicant: Dirk Tobben ,  Bruno Spuler ,  Martin Gutsche ,  Peter Weigand

Inventor： Dirk Tobben ,  Bruno Spuler ,  Martin Gutsche ,  Peter Weigand

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/12 ,  H05K1/00 ,  H05K3/06 ,  H05K3/22 ,  H05K3/24 ,  H01L21/469 ,  H01L21/312

CPC classification number: H05K3/061 ,  H01L21/32139 ,  H01L21/76838 ,  H05K1/0284 ,  H05K2201/09018 ,  H05K2203/0585

Abstract: A method for forming a plurality of electrically conductive wires on a substrate. The method includes forming a relatively non-planar metal layer over a surface of the substrate. A self-planarizing material is deposited over the metal layer. The self-planarizing material forms a planarization layer over the surface of the metal layer. The planarization layer has a surface relatively planar compared to the relatively non-planar metal layer. A photoresist layer is deposited over the surface of the planarization layer. The photoresist layer is patterned with a plurality of grooves to form a mask with such grooves exposing underling portions of the planarization layer. The photoresist mask is used as a mask to etch grooves in the exposed portions of the planarization layer and thereby form a second mask. The second mask exposes underling portions of the relatively non-planar metal layer. The second mask is used to etch grooves in the relatively non-planar conductive metal layer and thereby form the plurality of electrically conductive wires in the metal layer. The wires are separated from each other by the grooves formed in the relatively non-planar metal layer. The planarization layer is formed by a spinning-on an organic polymer, for example an organic polymer having silicon, or a flowable oxide, or a hydrogensilsequioxane, or divinyl-siloxane-benzocyclobutene. The metal layer is etched using reactive ion etching. The planarization layer is removed using a wet chemical etch.

Abstract translation: 一种在基板上形成多根导电线的方法。 该方法包括在衬底的表面上形成相对非平面的金属层。 自平面化材料沉积在金属层上。 自平面化材料在金属层的表面上形成平坦化层。 与相对非平面的金属层相比，平坦化层具有相对平坦的表面。 在平坦化层的表面上沉积光致抗蚀剂层。 用多个凹槽对光致抗蚀剂层进行图案化以形成掩模，该掩模具有暴露平坦化层的下部的这种凹槽。 光致抗蚀剂掩模用作掩模以蚀刻平坦化层的暴露部分中的凹槽，从而形成第二掩模。 第二掩模暴露相对非平面金属层的下层部分。 第二掩模用于蚀刻相对非平面导电金属层中的凹槽，从而在金属层中形成多个导电线。 电线通过在相对非平面的金属层中形成的凹槽彼此分离。 平坦化层是通过旋涂有机聚合物，例如具有硅的有机聚合物，或可流动的氧化物，或氢化二烷基锡，或二乙烯基 - 硅氧烷 - 苯并环丁烯等形成的。 使用反应离子蚀刻蚀刻金属层。 使用湿化学蚀刻去除平坦化层。

公开(公告)号：US6046503A

公开(公告)日：2000-04-04

申请号：US938072

申请日：1997-09-26

Applicant: Peter Weigand ,  Dirk Tobben

Inventor： Peter Weigand ,  Dirk Tobben

IPC: H05K3/46 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H05K1/00 ,  H05K1/02 ,  H01L23/48 ,  H01L23/52 ,  H01L29/00 ,  H01L29/40

CPC classification number: H01L23/5329 ,  H01L2924/0002 ,  H05K1/0201 ,  H05K3/4644 ,  H05K3/4676

Abstract: A multi-level integrated circuit metalization system having a composite dielectric layer comprising a layer 22 of diamond or sapphire. A plurality of patterned metalization layers is disposed over a semiconductor substrate 10. A composite dielectric layer is disposed between a pair of the metalization layers. The composite dielectric layer 22 comprises a layer of diamond or sapphire. The diamond or sapphire layer has disposed on a surface thereof one of the patterned metalization layers. A conductive via 34 passes through the composite layer. One end of the conductive via is in contact with diamond or sapphire layer. The diamond or sapphire layer conducts heat laterally along from the metalization layer disposed thereon to a heat sink provided by the conductive via. The patterned diamond or sapphire layer provides a mask during the second metalization deposition. Thus, the leads of the next metalization layer will be deposited directly on the diamond or sapphire layer which will serve as an etch stop during the metal etching process.

Abstract translation: 一种具有包括金刚石或蓝宝石层22的复合介电层的多级集成电路金属化系统。 多个图案化金属化层设置在半导体衬底10的上方。复合电介质层设置在一对金属化层之间。 复合介电层22包括一层金刚石或蓝宝石。 金刚石或蓝宝石层在其表面上设置有图案化的金属化层之一。 导电通孔34通过复合层。 导电通孔的一端与金刚石或蓝宝石层接触。 金刚石或蓝宝石层沿着设置在其上的金属化层横向导热至由导电通孔提供的散热片。 图案化的金刚石或蓝宝石层在第二次金属化沉积期间提供掩模。 因此，下一个金属化层的引线将直接沉积在金刚石或蓝宝石层上，该金属或蓝宝石层将在金属蚀刻工艺期间用作蚀刻停止层。

公开(公告)号：US5963837A

公开(公告)日：1999-10-05

申请号：US846924

申请日：1997-04-30

Applicant: Matthias Ilg ,  Dirk Tobben ,  Peter Weigand

Inventor： Matthias Ilg ,  Dirk Tobben ,  Peter Weigand

IPC: H01L21/3205 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/768 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L21/76819 ,  H01L21/31051 ,  H01L21/31053

Abstract: A method for planarizing a semiconductor structure having a first surface region with a high aspect ratio topography and a second surface region with a low aspect ratio topography. A flowable material is deposited over the first and second surface regions of the structure. A portion of the material fills gaps in the high aspect ratio topography to form a substantially planar surface over the high aspect ratio topography. A doped layer, for example phosphorus doped glass, is formed over the flowable oxide material. The doped layer is disposed over the high aspect ratio and over the low aspect ratio regions. Upper surface portions over the low aspect ratio region are higher than an upper surface of the flowable material. The upper portion of the doped layer is removed over both the first and second surface portions to form a layer with a substantially planar surface above both the high aspect ratio region and the low aspect ratio region. The method is used for filling gaps, such as gaps between adjacent gate electrodes formed in a gate electrode surface region of a semiconductor structure.

Abstract translation: 一种用于平面化具有高纵横比拓扑的第一表面区域和具有低纵横比拓扑的第二表面区域的半导体结构的方法。 可流动材料沉积在结构的第一和第二表面区域上。 材料的一部分填充高纵横比拓扑中的间隙，以在高纵横比拓扑上形成基本平坦的表面。 在可流动氧化物材料上形成掺杂层，例如磷掺杂玻璃。 掺杂层设置在高纵横比和低纵横比区域之上。 低纵横比区域上的上表面部分高于可流动材料的上表面。 在第一和第二表面部分上去除掺杂层的上部，以形成在高纵横比区域和低纵横比区域之上具有基本平坦表面的层。 该方法用于填充间隙，例如形成在半导体结构的栅电极表面区域中的相邻栅电极之间的间隙。

公开(公告)号：US5937541A

公开(公告)日：1999-08-17

申请号：US929711

申请日：1997-09-15

Applicant: Peter Weigand ,  Naohiro Shoda

Inventor： Peter Weigand ,  Naohiro Shoda

IPC: G01K13/02 ,  H01J37/32 ,  H01L21/00 ,  H01L21/027 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/66 ,  F26B21/00

CPC classification number: H01L21/67248 ,  H01J37/32522 ,  H01J37/3299 ,  H01L21/67109 ,  H01J2237/2001 ,  H01L22/12 ,  H01L2924/0002

Abstract: Apparatus and method are provided for obtaining improved measurement and control of the temperature of a semiconductor wafer (W) during processing. The apparatus includes a chuck for holding a wafer during processing, a coolant gas supply (16), and a temperature sensing arrangement for measuring and controlling the temperature of the wafer during processing. A top face of the chuck (22) over which the wafer is positioned, is configured with a plurality of holes (34) into which the coolant gas, such as helium, is admitted at controlled rate and pressure. The coolant gas passes through a narrow space (36) between the top face of the chuck and the underside of the wafer and is evacuated via an exhaust line (30) after being heated to (or nearly to) the temperature of the wafer. Temperature of the now-heated coolant gas is continuously measured by a temperature sensor arrangement which generates a signal controlling the pressure and flow of coolant gas to the wafer. Close control of the temperature of the wafer is thereby maintained continuously at a desired value during processing.

Abstract translation: 提供了用于在加工期间获得半导体晶片（W）的温度的改进的测量和控制的装置和方法。 该装置包括用于在处理期间保持晶片的卡盘，冷却剂气体供应装置（16）和用于在处理期间测量和控制晶片温度的温度感测装置。 夹具（22）的顶面位于晶片上，配置有多个孔（34），诸如氦气的冷却剂气体以受控的速率和压力进入其中。 冷却剂气体通过卡盘的顶面和晶片的下侧之间的狭窄空间（36），并且在加热到（或接近））晶片的温度之后通过排气管线（30）抽真空。 现在加热的冷却剂气体的温度通过温度传感器装置连续测量，温度传感器装置产生控制冷却剂气体到晶片的压力和流量的信号。 因此，在处理期间，将晶片的温度的关闭控制连续地保持在期望值。

公开(公告)号：US5899736A

公开(公告)日：1999-05-04

申请号：US933955

申请日：1997-09-19

Applicant: Peter Weigand ,  Dirk Tobben

Inventor： Peter Weigand ,  Dirk Tobben

IPC: H01L27/04 ,  H01L21/82 ,  H01L21/822 ,  H01L23/525 ,  H01L29/00

CPC classification number: H01L23/5256 ,  H01L2924/0002

Abstract: A method for fabricating an electrically blowable fuse on a semiconductor substrate. The method includes forming a fuse portion 102 on the semiconductor substrate. The fuse portion is configured to turn substantially non-conductive when a current exceeding a predefined current level passes through the fuse portion. The method also includes depositing a substantially conformal first layer 302 of dielectric material above the fuse portion and depositing a second layer 304 of dielectric material above the first layer, thereby forming a protrusion of dielectric material above the fuse portion. The second layer being different from the first layer. The method further includes performing chemical-mechanical polish on the protrusion to form an opening through the second layer above the protrusion. There is also included etching, in a substantially isotropic manner, a portion of the first layer through the opening to form a microcavity 502 about the fuse portion. The etching is substantially selective to the second layer and the fuse portion. Additionally, there is included depositing a substantially conformal third layer 606 of dielectric material above the second layer, thereby closing the opening in the second layer.

Abstract translation: 一种在半导体衬底上制造可电熔熔断器的方法。 该方法包括在半导体衬底上形成熔丝部分102。 保险丝部分被配置为当超过预定电流水平的电流通过熔丝部分时基本上不导通。 该方法还包括在熔丝部分上沉积基本上保形的介电材料第一层302，并在第一层上方沉积介电材料的第二层304，由此在熔丝部分上方形成电介质材料的突起。 第二层与第一层不同。 该方法还包括在突起上执行化学机械抛光以形成通过突起上方的第二层的开口。 还包括以基本上各向同性的方式蚀刻通过开口的第一层的一部分，以围绕熔丝部分形成微腔502。 蚀刻对第二层和熔丝部分基本上是选择性的。 另外，包括在第二层上方沉积介电材料的基本上保形的第三层606，从而封闭第二层中的开口。

公开(公告)号：US20120234841A1

公开(公告)日：2012-09-20

申请号：US13512374

申请日：2010-11-18

Applicant: Peter Weigand ,  Gunter Quass ,  Jens von Waaden

Inventor： Peter Weigand ,  Gunter Quass ,  Jens von Waaden

IPC: B65D90/48 ,  B65D90/64

CPC classification number: B65D81/38 ,  B65D90/48

Abstract: A port arrangement is configured for accessing a demountable component in an interior of an apparatus or container. The port arrangement includes an inner port having a port tube and forming a releasable connection with an internal component. The port tube of the inner port is guided through an outer port that is to an outer jacket.

Abstract translation: 端口布置被配置为访问装置或容器的内部中的可拆卸部件。 端口装置包括具有端口管并且与内部部件形成可释放连接的内部端口。 内部端口的端口管被引导通过外部外部外部端口。