公开(公告)号：US06184091B2

公开(公告)日：2001-02-06

申请号：US09241756

申请日：1999-02-01

Applicant: Ulrike Gruening ,  Jochen Beintner ,  Dirk Tobben ,  Gill Lee ,  Oswald Spindler ,  Zvonimir Gabric

Inventor： Ulrike Gruening ,  Jochen Beintner ,  Dirk Tobben ,  Gill Lee ,  Oswald Spindler ,  Zvonimir Gabric

IPC: H01L21336

CPC classification number: H01L27/10864 ,  H01L21/02126 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/31612 ,  H01L27/10876

Abstract: A method for controlling isolation layer thickness in trenches for semiconductor devices includes the steps of providing a trench having a conductive material formed therein, forming a liner on sidewalls of the trench above the conductive material, depositing a selective oxide deposition layer on the buried strap and the sidewalls, the selective oxide deposition layer selectively growing at an increased rate on the conductive material than on the liner of the sidewalls and top surface and removing the selective oxide deposition layer except for a portion in contact with the conductive to form an isolation layer on the conductive material in the trench. A method for fabricating vertical transistors by recessing a substrate to permit increased overlap between a transistor channel and buried strap outdiffusion when the transistor is formed is also included. A semiconductor device is also disclosed.

公开(公告)号：US6103456A

公开(公告)日：2000-08-15

申请号：US120629

申请日：1998-07-22

Applicant: Dirk Tobben ,  Gill Yong Lee

Inventor： Dirk Tobben ,  Gill Yong Lee

IPC: H01L21/3205 ,  G03F7/09 ,  H01L21/027 ,  H01L21/311 ,  H01L21/318 ,  H01L21/768 ,  G03F7/00

CPC classification number: H01L21/0276 ,  H01L21/31144 ,  H01L21/76807 ,  G03F7/091

Abstract: A method of forming a patterned conductive multilayer arrangement on a semiconductor substrate is provided which prevents photoresist poisoning by reactive nitrogenous substances from a silicon oxynitride layer forming a dielectric antireflective coating (DARC) for an overlying photoresist layer. The substrate has a first level conductive layer, e.g., of a metal, disposed in a region thereon, and is coated in turn with a dielectric insulation layer, e.g., of silicon dioxide, which overlies the first level conductive layer region, a dielectric antireflective coating (DARC) silicon oxynitride layer, an essentially reactive nitrogenous substance-free dielectric spacer layer, e.g., of spin-on glass (SOG), and a photoresist layer. The dielectric spacer layer prevents reactive nitrogenous substance transport therethrough from the DARC silicon oxynitride layer to the photoresist layer, thereby preventing poisoning of the photoresist layer. The photoresist layer is exposed and developed to uncover pattern portions of the dielectric spacer layer. The uncovered portions of the dielectric spacer layer and corresponding portions of the DARC silicon oxynitride layer are removed together, and then corresponding portions of the insulation layer, e.g., by a pair of tandem etching steps, to expose portions of the first level conductive layer for subsequent metallization.

Abstract translation: 提供了一种在半导体衬底上形成图案化导电多层布置的方法，其防止由形成用于覆盖光致抗蚀剂层的介电抗反射涂层（DARC）的氧氮化硅层的反应性含氮物质的光致抗蚀剂中毒。 衬底具有设置在其上的区域中的第一级导电层，例如金属，并且依次用诸如覆盖在第一级导电层区域上的二氧化硅的介电绝缘层，电介质抗反射 涂覆（DARC）氮氧化硅层，例如旋涂玻璃（SOG）和光致抗蚀剂层的基本上无活性的无氮物质电介质间隔层。 电介质隔离层防止反应性含氮物质从DARC氧氮化硅层传输到光致抗蚀剂层，从而防止光致抗蚀剂层的中毒。 光致抗蚀剂层被曝光和显影以露出介电间隔层的图案部分。 介质间隔层的未覆盖部分和DARC氮氧化硅层的对应部分一起被去除，然后去除绝缘层的相应部分，例如通过一对串联蚀刻步骤，以暴露第一级导电层的部分 随后的金属化。

公开(公告)号：US06015988A

公开(公告)日：2000-01-18

申请号：US197391

申请日：1998-11-20

Applicant: Dirk Tobben ,  Peter Weigand

Inventor： Dirk Tobben ,  Peter Weigand

IPC: H01L27/04 ,  B81B3/00 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/72

CPC classification number: B81C1/00111 ,  H01L27/10852 ,  H01L28/87 ,  H01L28/91 ,  B81C2201/0109 ,  B81C2201/0159 ,  H01L28/88 ,  H01L28/92

Abstract: A method for forming a microstructure includes photolithographically forming a vertically extending post on a portion of a surface of a substrate to provide a first structure. A flowable, sacrificial material is deposited over a surface of the first structure. The flowable, sacrificial materially flows off the top surface and sidewall portions of the post onto adjacent portions of the surface of the substrate to provide a second structure. A non-sacrificial material is deposited over a surface of the second structure. The non-sacrificial material is deposited to conform to the surface of the second structure. The non-sacrificial is deposited over the sacrificial material, over the sidewall portions and over the top surface of the post. The deposited sacrificial material is selectively removed while the non-sacrificial material remains to form a third structure with a horizontal member provided by the non-sacrificial material. The horizontal member is supported a predetermined distance above the surface of the substrate by a lower portion of the post. The flowable material is a flowable oxide, for example, hydrogensilsesquioxane glass, and the post has a width less than 20 .mu.m. The resulting structure, formed with a single photolithographic step, is used for supporting a capacitor deposited over it. The capacitor is formed as a sequence of deposition steps; i.e., depositing a first conductive layer over a surface of the support structure; depositing a dielectric layer over the conductive layer; and depositing a second conductive layer over the dielectric layer.

Abstract translation: 一种用于形成微结构的方法包括光刻地形成垂直延伸的柱体，以在衬底表面的一部分上提供第一结构。 可流动的牺牲材料沉积在第一结构的表面上。 可流动的牺牲物质地从柱的顶表面和侧壁部分流出到衬底的表面的相邻部分上以提供第二结构。 非牺牲材料沉积在第二结构的表面上。 沉积非牺牲材料以符合第二结构的表面。 非牺牲材料沉积在牺牲材料上，在侧壁部分上方并在柱的顶表面上方。 选择性地去除沉积的牺牲材料，同时非牺牲材料保留以形成具有由非牺牲材料提供的水平构件的第三结构。 水平构件通过柱的下部支撑在基板的表面上方预定距离。 可流动材料是可流动的氧化物，例如氢倍半硅氧烷玻璃，柱的宽度小于20μm。 用单个光刻步骤形成的所得结构用于支撑沉积在其上的电容器。 电容器形成为一系列沉积步骤; 即在支撑结构的表面上沉积第一导电层; 在导电层上沉积介电层; 以及在所述电介质层上沉积第二导电层。

公开(公告)号：US06261950B1

公开(公告)日：2001-07-17

申请号：US09420402

申请日：1999-10-18

Applicant: Dirk Tobben ,  Jeffrey Gambino

Inventor： Dirk Tobben ,  Jeffrey Gambino

IPC: H01L214763

CPC classification number: H01L23/5226 ,  H01L21/76886 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for connecting metal structures with self-aligned metal caps, in accordance with the invention, includes providing a metal structure in a first dielectric layer. The metal structure and the first dielectric layer share a substantially planar surface. A cap metal is selectively depositing on the metal structure such that the cap metal is deposited only on the metal structure. A second dielectric layer is formed over the cap metal. The second dielectric layer is opened to form a via terminating in the cap metal. A conductive material is deposited in the via to provide a contact to the metal structure through the cap metal.

Abstract translation: 根据本发明的用于连接具有自对准金属盖的金属结构的方法包括在第一电介质层中提供金属结构。 金属结构和第一介电层共享基本平坦的表面。 帽金属选择性地沉积在金属结构上，使得金属金属仅沉积在金属结构上。 在帽金属上方形成第二电介质层。 打开第二电介质层以形成端接在盖金属中的通孔。 导电材料沉积在通孔中以通过盖金属提供与金属结构的接触。

公开(公告)号：US06177698B1

公开(公告)日：2001-01-23

申请号：US09461599

申请日：1999-12-15

Applicant: Ulrike Gruening ,  Jochen Beintner ,  Dirk Tobben ,  Gill Lee ,  Oswald Spindler ,  Zvonimir Gabric

Inventor： Ulrike Gruening ,  Jochen Beintner ,  Dirk Tobben ,  Gill Lee ,  Oswald Spindler ,  Zvonimir Gabric

IPC: H01L27108

CPC classification number: H01L27/10864 ,  H01L21/02126 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/31612 ,  H01L27/10876

Abstract: A method for controlling isolation layer thickness in trenches for semiconductor devices includes the steps of providing a trench having a conductive material formed therein, forming a liner on sidewalls of the trench above the conductive material, depositing a selective oxide deposition layer on the buried strap and the sidewalls, the selective oxide deposition layer selectively growing at an increased rate on the conductive material than on the liner of the sidewalls and top surface and removing the selective oxide deposition layer except for a portion in contact with the conductive to form an isolation layer on the conductive material in the trench. A method for fabricating vertical transistors by recessing a substrate to permit increased overlap between a transistor channel and buried strap outdiffusion when the transistor is formed is also included. A semiconductor device is also disclosed.

Abstract translation: 用于控制用于半导体器件的沟槽中的隔离层厚度的方法包括以下步骤：提供在其中形成的导电材料的沟槽，在导电材料上方的沟槽的侧壁上形成衬垫，在掩埋带上沉积选择性氧化物沉积层， 侧壁，选择性氧化物沉积层以比在侧壁和顶表面的衬垫上更高的速率选择性地在导电材料上生长，并且除去与导电体接触的部分之外的选择性氧化物沉积层以形成隔离层 沟槽中的导电材料。 还包括当晶体管形成时，通过使衬底凹陷来制造垂直晶体管以允许晶体管沟道和掩埋带外扩散之间的重叠增加的方法。 还公开了一种半导体器件。

公开(公告)号：US06245629B1

公开(公告)日：2001-06-12

申请号：US09276027

申请日：1999-03-25

Applicant: Dirk Tobben

Inventor： Dirk Tobben

IPC: H01L2120

CPC classification number: H01L21/76897 ,  H01L21/76831 ,  H01L23/485

Abstract: A method for forming source/drain contacts to source/drain regions of an array of transistors. The method includes providing a semiconductor body with a gate oxide layer over the surface of the semiconductor body. The gate oxide layer extends over active areas in the semiconductor body. Gate stacks are provided on the gate oxide layer in columns across the rows of active areas. A dielectric material is deposited over the surface of the provided semiconductor body. Vias are etched through the dielectric material over source/drain regions in portions of the active area between the columns of gate stacks. First portion of sidewalls of such vias are formed over portions of adjacent columns of the gate stacks and second portions of the sidewalls of such vias are formed between adjacent columns of the gate stacks. The vias expose portions of the gate oxide layer over the source/drain regions. Source/drain contacts are formed in the vias, such formation comprising: forming spacers on the sidewalls of the regions of dielectric material; exposing the exposed portions of the gate oxide to an etch to remove such exposed portions of the gate oxide layer, such etch etching the gate oxide at a substantially higher etch rate that to the spacers; and forming conductive materials on the spacers and in contact with the source/drain regions.

Abstract translation: 一种用于将晶体管阵列的源极/漏极区域形成源极/漏极接触的方法。 该方法包括在半导体本体的表面上提供具有栅极氧化物层的半导体本体。 栅极氧化物层在半导体本体中的有源区域上延伸。 栅极堆叠被提供在栅极氧化物层上跨越有效区域的列。 介电材料沉积在所提供的半导体本体的表面上。 在栅极堆叠列之间的有源区域的部分中，通过源极/漏极区域在绝缘材料上蚀刻通孔。 这种通孔的侧壁的第一部分形成在栅堆叠的相邻列的部分上，并且这些通孔的侧壁的第二部分形成在相邻的栅叠层之间。 通孔在栅极/漏极区域上露出栅极氧化物层的部分。 源极/漏极触点形成在通孔中，这种形成包括：在介电材料的区域的侧壁上形成间隔物; 将栅极氧化物的暴露部分暴露于蚀刻以去除栅极氧化物层的这种暴露部分，这种蚀刻以相对于间隔物的基本更高的蚀刻速率蚀刻栅极氧化物; 以及在间隔物上形成导电材料并与源极/漏极区域接触。

公开(公告)号：US6046503A

公开(公告)日：2000-04-04

申请号：US938072

申请日：1997-09-26

Applicant: Peter Weigand ,  Dirk Tobben

Inventor： Peter Weigand ,  Dirk Tobben

IPC: H05K3/46 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H05K1/00 ,  H05K1/02 ,  H01L23/48 ,  H01L23/52 ,  H01L29/00 ,  H01L29/40

CPC classification number: H01L23/5329 ,  H01L2924/0002 ,  H05K1/0201 ,  H05K3/4644 ,  H05K3/4676

Abstract: A multi-level integrated circuit metalization system having a composite dielectric layer comprising a layer 22 of diamond or sapphire. A plurality of patterned metalization layers is disposed over a semiconductor substrate 10. A composite dielectric layer is disposed between a pair of the metalization layers. The composite dielectric layer 22 comprises a layer of diamond or sapphire. The diamond or sapphire layer has disposed on a surface thereof one of the patterned metalization layers. A conductive via 34 passes through the composite layer. One end of the conductive via is in contact with diamond or sapphire layer. The diamond or sapphire layer conducts heat laterally along from the metalization layer disposed thereon to a heat sink provided by the conductive via. The patterned diamond or sapphire layer provides a mask during the second metalization deposition. Thus, the leads of the next metalization layer will be deposited directly on the diamond or sapphire layer which will serve as an etch stop during the metal etching process.

Abstract translation: 一种具有包括金刚石或蓝宝石层22的复合介电层的多级集成电路金属化系统。 多个图案化金属化层设置在半导体衬底10的上方。复合电介质层设置在一对金属化层之间。 复合介电层22包括一层金刚石或蓝宝石。 金刚石或蓝宝石层在其表面上设置有图案化的金属化层之一。 导电通孔34通过复合层。 导电通孔的一端与金刚石或蓝宝石层接触。 金刚石或蓝宝石层沿着设置在其上的金属化层横向导热至由导电通孔提供的散热片。 图案化的金刚石或蓝宝石层在第二次金属化沉积期间提供掩模。 因此，下一个金属化层的引线将直接沉积在金刚石或蓝宝石层上，该金属或蓝宝石层将在金属蚀刻工艺期间用作蚀刻停止层。

公开(公告)号：US6033977A

公开(公告)日：2000-03-07

申请号：US884729

申请日：1997-06-30

Applicant: Martin Gutsche ,  Dirk Tobben

Inventor： Martin Gutsche ,  Dirk Tobben

IPC: H01L21/28 ,  H01L21/768 ,  H01L21/4763

CPC classification number: H01L21/76807 ,  H01L2221/1026

Abstract: A method for manufacturing a dual damascene structure includes the use of a sacrificial stud and provides an improved defined edge on the interface between the conductive line openings and the via openings.

Abstract translation: 制造双镶嵌结构的方法包括使用牺牲柱，并且在导电线开口和通孔开口之间的界面上提供改进的限定边缘。

公开(公告)号：US6001740A

公开(公告)日：1999-12-14

申请号：US187165

申请日：1998-11-06

Applicant: Kathryn H. Varian ,  Dirk Tobben ,  Matthew Sendelbach

Inventor： Kathryn H. Varian ,  Dirk Tobben ,  Matthew Sendelbach

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/3205 ,  H01L21/762 ,  H01L21/768 ,  H01L23/522 ,  H01L21/00

CPC classification number: H01L21/76229 ,  H01L21/31053

Abstract: A substantially planar surface is produced from a non-conformal device layer formed over a complex topography, which includes narrow features with narrow gaps and wide features and wide gaps. A conformal layer is deposited over the non-conformal layer. The surface is then polished to expose the non-conformal layer over the wide features. An etch selective to the non-conformal layer is then used to substantially remove the non-conformal layer over the wide features. The conformal layer is then removed, exposing the non-conformal layer. The thickness of the non-conformal layer is now more uniform as compared to before. This enables the polish to produce a planar surface with reduced dishing in the wide spaces.

Abstract translation: 基本平坦的表面由复杂形貌上形成的非保形装置层产生，其包括具有窄间隙和宽特征以及宽间隙的窄特征。 保形层沉积在非保形层上。 然后抛光表面以在宽的特征上露出非共形层。 然后对非共形层进行选择性蚀刻，以便在宽的特征上基本上去除非共形层。 然后去除保形层，暴露非保形层。 与以前相比，非保形层的厚度现在更均匀。 这使得抛光剂能够在宽的空间中产生具有减小的凹陷的平坦表面。

公开(公告)号：US5963837A

公开(公告)日：1999-10-05

申请号：US846924

申请日：1997-04-30

Applicant: Matthias Ilg ,  Dirk Tobben ,  Peter Weigand

Inventor： Matthias Ilg ,  Dirk Tobben ,  Peter Weigand

IPC: H01L21/3205 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/768 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L21/76819 ,  H01L21/31051 ,  H01L21/31053

Abstract: A method for planarizing a semiconductor structure having a first surface region with a high aspect ratio topography and a second surface region with a low aspect ratio topography. A flowable material is deposited over the first and second surface regions of the structure. A portion of the material fills gaps in the high aspect ratio topography to form a substantially planar surface over the high aspect ratio topography. A doped layer, for example phosphorus doped glass, is formed over the flowable oxide material. The doped layer is disposed over the high aspect ratio and over the low aspect ratio regions. Upper surface portions over the low aspect ratio region are higher than an upper surface of the flowable material. The upper portion of the doped layer is removed over both the first and second surface portions to form a layer with a substantially planar surface above both the high aspect ratio region and the low aspect ratio region. The method is used for filling gaps, such as gaps between adjacent gate electrodes formed in a gate electrode surface region of a semiconductor structure.

Abstract translation: 一种用于平面化具有高纵横比拓扑的第一表面区域和具有低纵横比拓扑的第二表面区域的半导体结构的方法。 可流动材料沉积在结构的第一和第二表面区域上。 材料的一部分填充高纵横比拓扑中的间隙，以在高纵横比拓扑上形成基本平坦的表面。 在可流动氧化物材料上形成掺杂层，例如磷掺杂玻璃。 掺杂层设置在高纵横比和低纵横比区域之上。 低纵横比区域上的上表面部分高于可流动材料的上表面。 在第一和第二表面部分上去除掺杂层的上部，以形成在高纵横比区域和低纵横比区域之上具有基本平坦表面的层。 该方法用于填充间隙，例如形成在半导体结构的栅电极表面区域中的相邻栅电极之间的间隙。