公开(公告)号：US09546090B1

公开(公告)日：2017-01-17

申请号：US14826449

申请日：2015-08-14

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Jia Jie Xia ,  Nagarajan Ranganathan ,  Rakesh Kumar ,  Aveek Nath Chatterjee

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/007 ,  B81B2201/016 ,  B81B2201/0271 ,  B81B2207/015 ,  B81B2207/07 ,  B81C1/00246 ,  B81C1/00253 ,  B81C2201/013 ,  B81C2201/019 ,  B81C2201/053 ,  B81C2203/0735 ,  B81C2203/0771 ,  B81C2203/0792

Abstract: Integrated MEMS-CMOS devices and methods for fabricating MEMS devices and CMOS devices are provided. An exemplary method for fabricating a MEMS device and a CMOS device includes forming the CMOS device in and/or over a first side of a semiconductor substrate. Further, the method includes forming the MEMS device in and/or under a second side of the semiconductor substrate. The second side of the semiconductor substrate is opposite the first side of the semiconductor substrate.

Abstract translation: 提供了用于制造MEMS器件和CMOS器件的集成MEMS-CMOS器件和方法。 用于制造MEMS器件和CMOS器件的示例性方法包括在半导体衬底的第一侧中和/或之上形成CMOS器件。 此外，该方法包括在半导体衬底的第二面内和/或下方形成MEMS器件。 半导体衬底的第二面与半导体衬底的第一侧相对。

公开(公告)号：US09272899B2

公开(公告)日：2016-03-01

申请号：US14591896

申请日：2015-01-07

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Rama Krishna Kotlanka ,  Rakesh Kumar ,  Premachandran Chirayarikathuveedu Sankarapillai ,  Huamao Lin ,  Pradeep Yelehanka

IPC: H01L23/48 ,  H01L25/065 ,  B81B7/00 ,  H01L21/50 ,  B81C1/00 ,  B81C3/00 ,  H01L23/522

CPC classification number: B81B7/0006 ,  B81C1/00269 ,  B81C3/001 ,  B81C2201/0115 ,  H01L21/50 ,  H01L23/481 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A bonded device having at least one porosified surface is disclosed. The porosification process introduces nanoporous holes into the microstructure of the bonding surfaces of the devices. The material property of a porosified material is softer as compared to a non-porosified material. For the same bonding conditions, the use of the porosified bonding surfaces enhances the bond strength of the bonded interface as compared to the non-porosified material.

公开(公告)号：US11706987B2

公开(公告)日：2023-07-18

申请号：US16722137

申请日：2019-12-20

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： You Qian ,  Joan Josep Giner De Haro ,  Rakesh Kumar

IPC: H01L41/314 ,  H10N30/072 ,  H10N30/074 ,  H10N30/85 ,  H10N30/87

CPC classification number: H10N30/072 ,  H10N30/074 ,  H10N30/85 ,  H10N30/87

Abstract: A semiconductor device may include: a substrate wafer, a bonding layer at least partially covering a front surface of the substrate wafer, a plurality of silicon pillars bonded to the front surface of the substrate wafer by the bonding layer, a single-crystal piezoelectric film having a first surface and an opposing second surface, a top electrode arranged adjacent to the first surface of the single-crystal piezoelectric film, and a bottom electrode arranged adjacent to the second surface of the single-crystal piezoelectric film. The single-crystal piezoelectric film may be supported by the plurality of silicon pillars such that the second surface of the piezoelectric film and the front surface of the substrate wafer enclose a cavity therebetween.

公开(公告)号：US10189705B1

公开(公告)日：2019-01-29

申请号：US15793965

申请日：2017-10-25

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Humberto Campanella Pineda ,  Anthony Kendall Stamper ,  You Qian ,  Sharath Poikayil Satheesh ,  Jeffrey C. Maling ,  Rakesh Kumar

IPC: B81C1/00 ,  B81B7/00

Abstract: An integrated monolithic device with a micro-electromechanical system (MEMS) and an integrated circuit (IC) and a method of forming thereof is disclosed. The monolithic device includes a substrate with IC components and a MEMS formed over the IC. A back-end-of-line (BEOL) dielectric having IC interconnect pads in a pad level is formed over the substrate. A MEMS is formed over the BEOL dielectric with the IC interconnect pads. The MEMS includes a MEMS stack having an active MEMS layer and patterned top and bottom MEMS electrodes formed on the top and bottom surfaces of the active MEMS layer. IC MEMS contact vias are formed at least partially through the active MEMS layer. IC MEMS contacts are formed in the IC MEMS contact vias in the active MEMS layer and configured to couple to the IC interconnect pads.

公开(公告)号：US10184951B2

公开(公告)日：2019-01-22

申请号：US15040681

申请日：2016-02-10

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Aveek Nath Chatterjee ,  Siddharth Chakravarty ,  Ramachandramurthy Pradeep Yelehanka ,  Rakesh Kumar

IPC: G01P15/125 ,  G01P15/09 ,  G01P15/08 ,  G01P15/18

Abstract: Three-axis monolithic microelectromechanical system (MEMS) accelerometers and methods for fabricating integrated capacitive and piezo accelerometers are provided. In an embodiment, a three-axis MEMS accelerometer includes a first sensing structure for sensing acceleration in a first direction. Further, the three-axis MEMS accelerometer includes a second sensing structure for sensing acceleration in a second direction perpendicular to the first direction. Also, the three-axis MEMS accelerometer includes a third sensing structure for sensing acceleration in a third direction perpendicular to the first direction and perpendicular to the second direction. At least one sensing structure is a capacitive structure and at least one sensing structure is a piezo structure.

公开(公告)号：US20180170748A1

公开(公告)日：2018-06-21

申请号：US15899785

申请日：2018-02-20

Applicant: Globalfoundries Singapore Pte. Ltd.

Inventor： Siddharth Chakravarty ,  Rakesh Kumar ,  Pradeep Yelehanka

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00293 ,  B81B7/0074 ,  B81B2203/0315 ,  B81C2201/0105 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2203/0136

Abstract: Semiconductor devices with enclosed cavities and methods for fabricating semiconductor devices with enclosed cavities are provided. In an embodiment, a method for fabricating a semiconductor device with a cavity includes providing a substrate terminating at an uppermost surface and forming a sacrificial structure over the uppermost substrate of the substrate. The method includes forming a device structure overlying a lower portion of the sacrificial structure, overlying the uppermost surface of the substrate, and underlying an upper portion of the sacrificial structure. The method also includes depositing a permeable layer over the sacrificial structure, the device structure and the substrate. Further, the method includes etching the sacrificial structure through the permeable layer to form the cavity, wherein the cavity has an outer surface completely bounded by the substrate, the device structure, and the permeable layer.

公开(公告)号：US20170366107A1

公开(公告)日：2017-12-21

申请号：US15185642

申请日：2016-06-17

Applicant: Globalfoundries Singapore Pte. Ltd.

Inventor： Aveek Nath Chatterjee ,  Rakesh Kumar

IPC: H02N2/18 ,  H02N2/00 ,  H03H9/02 ,  H03H9/17 ,  H03H3/007 ,  H03H9/15

CPC classification number: H02N2/188 ,  H02N2/22 ,  H03H3/0077 ,  H03H9/02338 ,  H03H9/17 ,  H03H2009/02165 ,  H03H2009/155

Abstract: Micro-Electro-Mechanical System (MEMS) devices for harvesting sound energy and methods for fabricating MEMS devices for harvesting sound energy are provided. In an embodiment, a method for fabricating a MEMS device for harvesting sound energy includes forming a pressure sensitive MEMS structure disposed over a semiconductor substrate and including a suspended structure in a cavity. Further, the method includes etching the semiconductor substrate to form an acoustic port through the semiconductor substrate configured to allow acoustic pressure to deflect the suspended structure.

公开(公告)号：US20170227570A1

公开(公告)日：2017-08-10

申请号：US15040681

申请日：2016-02-10

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Aveek Nath Chatterjee ,  Siddharth Chakravarty ,  Ramachandramurthy Pradeep Yelehanka ,  Rakesh Kumar

IPC: G01P15/125 ,  G01P15/08 ,  G01P15/18 ,  G01P15/09

CPC classification number: G01P15/125 ,  B81B3/0062 ,  B81B2201/0235 ,  B81B2203/053 ,  B81B2203/055 ,  G01P15/0802 ,  G01P15/09 ,  G01P15/18

Abstract: Three-axis monolithic microelectromechanical system (MEMS) accelerometers and methods for fabricating integrated capacitive and piezo accelerometers are provided. In an embodiment, a three-axis MEMS accelerometer includes a first sensing structure for sensing acceleration in a first direction. Further, the three-axis MEMS accelerometer includes a second sensing structure for sensing acceleration in a second direction perpendicular to the first direction. Also, the three-axis MEMS accelerometer includes a third sensing structure for sensing acceleration in a third direction perpendicular to the first direction and perpendicular to the second direction. At least one sensing structure is a capacitive structure and at least one sensing structure is a piezo structure.

公开(公告)号：US20170174507A1

公开(公告)日：2017-06-22

申请号：US14973319

申请日：2015-12-17

Applicant: Globalfoundries Singapore Pte. Ltd.

Inventor： Siddharth Chakravarty ,  Rakesh Kumar ,  Pradeep Yelehanka

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00293 ,  B81B7/0074 ,  B81B2203/0315 ,  B81C2201/0105 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2203/0136

Abstract: Semiconductor devices with enclosed cavities and methods for fabricating semiconductor devices with enclosed cavities are provided. In an embodiment, a method for fabricating a semiconductor device with a cavity includes forming a sacrificial structure in and/or over a substrate. The method includes depositing a permeable layer over the sacrificial structure and the substrate. Further, the method includes etching the sacrificial structure through the permeable layer to form the cavity bounded by the substrate and the permeable layer.

公开(公告)号：US20170092523A1

公开(公告)日：2017-03-30

申请号：US14868645

申请日：2015-09-29

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Ying Yu ,  Jianbo Sun ,  Derui Yin ,  Yelehanka Ramachandramurthy Pradeep ,  Rakesh Kumar

IPC: H01L21/68 ,  H01L23/544

CPC classification number: H01L21/681 ,  G02B6/122 ,  G02B6/132 ,  G02B6/136 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453

Abstract: Methods of producing integrated circuits with interposers and integrated circuits produced from such methods are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming a base layer overlying a substrate, and forming an alignment mark overlying the base layer. A first layer is formed overlying the base layer and the alignment mark, and the first layer has a first layer thickness. A second layer is formed overlying the first layer, where the second layer has a second layer thickness and where a combined thickness of the first and second layer thicknesses is from about 2 to about 50 micrometers. A second component is formed from the second layer.