公开(公告)号：US20160380181A1

公开(公告)日：2016-12-29

申请号：US14947649

申请日：2015-11-20

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Martin Gruber ,  Rainer Markus Schaller ,  Franz Jost ,  Stefan Mieslinger ,  Liu Chen ,  Toni Salminen ,  Giuliano Angelo Babulano ,  Jens Oetjen ,  Markus Dinkel

IPC: H01L43/02 ,  G01R33/09 ,  G01R33/07 ,  H01L43/06 ,  H01L43/08

CPC classification number: H01L43/02 ,  G01R33/07 ,  G01R33/09 ,  H01L27/22 ,  H01L43/065 ,  H01L43/08 ,  H01L2224/0603 ,  H01L2224/37147 ,  H01L2224/37599 ,  H01L2224/40 ,  H01L2224/48137 ,  H01L2224/4903 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2924/00014

Abstract: A semiconductor package includes a semiconductor die attached to a substrate and a magnetic field sensor included as part of the same semiconductor package as the semiconductor die and positioned in close proximity to a current pathway of the semiconductor die so that the magnetic field sensor can sense a magnetic field produced by current flowing in the current pathway. The magnetic field sensor includes a first magnetic field sensing component galvanically isolated from the current pathway and positioned so that a magnetic field produced by current flowing in the current pathway impinges on the first magnetic field sensing component in a first direction. The magnetic field sensor also includes a second magnetic field sensing component galvanically isolated from the current pathway and positioned so that the magnetic field impinges on the second magnetic field sensing component in a second direction different than the first direction.

Abstract translation: 半导体封装包括附接到衬底的半导体管芯和作为与半导体管芯相同的半导体封装的一部分的磁场传感器，并且位于靠近半导体管芯的电流通路的位置，使得磁场传感器可感测 电流在电流通路中流动产生的磁场。 磁场传感器包括与电流通路电隔离的第一磁场感测部件，并被定位成使得在电流通路中流动的电流产生的磁场沿第一方向冲击第一磁场感测部件。 磁场传感器还包括与电流路径电隔离并定位成使得磁场在不同于第一方向的第二方向上撞击在第二磁场感测部件上的第二磁场感测部件。

公开(公告)号：US11502042B2

公开(公告)日：2022-11-15

申请号：US16917947

申请日：2020-07-01

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Thomas Behrens ,  Martin Gruber ,  Thorsten Scharf ,  Peter Strobel

IPC: H01L21/301 ,  H01L21/46 ,  H01L21/78 ,  H01L23/544 ,  H01L23/00

Abstract: A method of mounting electronic components on one or more carrier bodies is disclosed. The method comprises providing a support body with at least one first alignment mark, mounting the one or more carrier bodies, each having at least one second alignment mark, on the support body by alignment between the at least one first alignment mark and the at least one second alignment mark. Thereafter, the method includes mounting the plurality of electronic components on a respective one of the one or more carrier bodies by alignment using the at least one second alignment mark.

公开(公告)号：US11367683B2

公开(公告)日：2022-06-21

申请号：US16453222

申请日：2019-06-26

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Ravi Keshav Joshi ,  Ralf Siemieniec ,  Thomas Basler ,  Martin Gruber ,  Jochen Hilsenbeck ,  Dethard Peters ,  Roland Rupp ,  Wolfgang Scholz

IPC: H01L23/532 ,  H01L29/16 ,  H01L21/768 ,  H01L23/00 ,  H01L29/45

Abstract: A silicon carbide device includes a silicon carbide substrate, a contact layer including nickel, silicon and aluminum, a barrier layer structure including titanium and tungsten, and a metallization layer including copper. The contact layer is located on the silicon carbide substrate. The contact layer is located between the silicon carbide substrate and at least a part of the barrier layer structure. The barrier layer structure is located between the silicon carbide substrate and the metallization layer.

公开(公告)号：US20210225744A1

公开(公告)日：2021-07-22

申请号：US17150739

申请日：2021-01-15

Applicant: Infineon Technologies AG

Inventor： Frank Singer ,  Marcus Boehm ,  Andreas Grassmann ,  Martin Gruber ,  Uwe Schindler

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: A package includes a carrier, an electronic component on the carrier, an encapsulant encapsulating at least part of the carrier and the electronic component, and at least one lead extending beyond the encapsulant and having a punched surface, wherein at least part of at least one side flank of the encapsulant has a sawn texture.

公开(公告)号：US20210166998A1

公开(公告)日：2021-06-03

申请号：US17176576

申请日：2021-02-16

Applicant: Infineon Technologies AG

Inventor： Thorsten Scharf ,  Martin Gruber ,  Josef Hoeglauer ,  Michael Juerss ,  Josef Maerz ,  Thorsten Meyer ,  Bun Kian Tay

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56

Abstract: A molded semiconductor package includes a lead frame having one or more first leads monolithically formed with a die pad and extending outward from the pad in a first direction. A semiconductor die is attached to the die pad at a first side of the die. A metal clip of a clip frame is attached to a power terminal at a second side of the die. One or more second leads monolithically formed with the metal clip extend outward from the clip in a second direction different than the first direction. A mold compound embeds the die. The first lead(s) and the second lead(s) are exposed at different sides of the mold compound and do not vertically overlap with one another. Within the mold compound, the clip transitions from a first level above the power terminal to a second level in a same plane as the leads.

公开(公告)号：US10886186B2

公开(公告)日：2021-01-05

申请号：US16365837

申请日：2019-03-27

Applicant: Infineon Technologies AG

Inventor： Thorsten Scharf ,  Ralf Otremba ,  Thomas Bemmerl ,  Irmgard Escher-Poeppel ,  Martin Gruber ,  Michael Juerss ,  Thorsten Meyer ,  Xaver Schloegel

IPC: H01L23/053 ,  H01L23/08 ,  H01L23/00 ,  H01L23/40

Abstract: A semiconductor package system comprises a semiconductor package and a cap. The semiconductor package comprises a die pad, a chip mounted or arranged to a first main face of the die pad and an encapsulation body encapsulating the chip and the die pad. The cap covers at least partly an exposed second main face of the die pad. The cap comprises a cap body of an electrically insulating and thermally conductive material and a fastening system fastening the cap to the semiconductor package. The fastening system extends from the cap body towards the encapsulation body or along a side surface of the semiconductor package.

公开(公告)号：US10079195B2

公开(公告)日：2018-09-18

申请号：US15292554

申请日：2016-10-13

Applicant: Infineon Technologies AG

Inventor： Wolfram Hable ,  Martin Gruber ,  Juergen Hoegerl

IPC: H01L23/12 ,  H01L23/373 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L25/18 ,  H02M3/158 ,  H02M5/293 ,  H02M5/297 ,  H02M7/217 ,  H02M7/537

CPC classification number: H01L23/3735 ,  H01L21/4882 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3135 ,  H01L24/24 ,  H01L24/32 ,  H01L24/45 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L25/18 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/92244 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H02M3/158 ,  H02M5/293 ,  H02M5/297 ,  H02M7/003 ,  H02M7/217 ,  H02M7/537 ,  H01L2224/45099

Abstract: A semiconductor chip package is disclosed. The package includes a carrier, a plurality of semiconductor chips disposed on the carrier, a first encapsulation layer disposed above the semiconductor chips. A metallization layer is disposed above the first encapsulation layer, the metallization layer including a plurality of first metallic areas forming electrical connections between selected ones of the semiconductor chips. A second encapsulation layer is disposed above the solder resist layer. A plurality of external connectors are provided, each one of the external connectors being connected with one of the first metallic areas and extending outwardly through a surface of the second encapsulation layer.

公开(公告)号：US10014275B2

公开(公告)日：2018-07-03

申请号：US15459151

申请日：2017-03-15

Applicant: Infineon Technologies AG

Inventor： Alexander Heinrich ,  Irmgard Escher-Poeppel ,  Martin Gruber ,  Andreas Munding ,  Catharina Wille

IPC: H01L23/00 ,  H01L25/00

CPC classification number: H01L24/81 ,  H01L24/09 ,  H01L24/16 ,  H01L24/85 ,  H01L25/50 ,  H01L2224/095 ,  H01L2224/16104 ,  H01L2224/16112 ,  H01L2224/16137 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01L2224/49113 ,  H01L2224/4912 ,  H01L2924/00014 ,  H01L2224/45099

Abstract: One aspect of the invention relates to a method for producing a chip assemblage. Two or more chip assemblies are produced in each case by cohesively and electrically conductively connecting an electrically conductive first compensation lamina to a first main electrode of a semiconductor chip. A control electrode interconnection structure is arranged in a free space between the chip assemblies. Electrically conductive connections are produced between the control electrode interconnection structure and control electrodes of the semiconductor chips of the individual chip assemblies. The chip assemblies are cohesively connected by means of a dielectric embedding compound.

公开(公告)号：US09857439B2

公开(公告)日：2018-01-02

申请号：US14994170

申请日：2016-01-13

Applicant: Infineon Technologies AG

Inventor： Franz Jost ,  Holger Wille ,  Martin Gruber

IPC: G01R33/02 ,  G01R33/09 ,  G01R33/00 ,  H01L43/12 ,  G06F1/00 ,  H01L21/00

CPC classification number: G01R33/091 ,  G01R33/0052 ,  G01R33/093 ,  G06F1/00 ,  G06F2101/00 ,  H01L21/00 ,  H01L43/12

Abstract: A sensor arrangement is provided. The sensor arrangement may include at least one sensor element having a first side and a second side opposite the first side and configured for sensing a magnetic field; and an electrically conductive line, wherein a first portion of the electrically conductive line may be arranged on the first side of the at least one sensor element and a second portion of the electrically conductive line may be arranged on the second side of the at least one sensor element in such a way that if a current is flowing through the electrically conductive line, the current has a first direction in the first portion and a second direction opposite the first direction in the second portion, such that a first magnetic field formed by the current in the first portion and a second magnetic field formed by the current in the second portion may at least partly add constructively at a sensing portion of the at least one sensor element.

公开(公告)号：US09140735B2

公开(公告)日：2015-09-22

申请号：US13886285

申请日：2013-05-03

Applicant: Infineon Technologies AG

Inventor： Martin Gruber ,  Angela Kessler

IPC: G01R27/08 ,  G01R27/14 ,  G01R31/26 ,  G01R15/18 ,  G01R31/28 ,  G01R3/00 ,  G01R1/20 ,  H05K1/16 ,  G01R13/34 ,  H05K3/06

CPC classification number: G01R27/14 ,  G01R1/203 ,  G01R3/00 ,  G01R13/347 ,  G01R15/181 ,  G01R31/2648 ,  G01R31/2884 ,  H05K1/0268 ,  H05K1/167 ,  H05K3/06 ,  H05K2201/09736 ,  H05K2201/10166 ,  H05K2203/092 ,  H05K2203/171

Abstract: A method of manufacturing an electronic circuit with an integrally formed capability of providing information indicative of a value of a current flowing in the electronic circuit, wherein the method comprises forming an electrically conductive wiring structure on a substrate, configuring a first section of the wiring structure for contributing to a predefined use function of the electronic circuit, and configuring a second section of the wiring structure for providing information indicative of the value of the current flowing in the electronic circuit upon applying a stimulus signal to the second section, wherein at least a part of the configuring of the first section and the configuring of the second section is performed simultaneously.

Abstract translation: 一种制造电子电路的方法，所述电子电路具有提供表示在所述电子电路中流动的电流的值的信息的整合能力，其中所述方法包括在基板上形成导电布线结构，构成所述布线结构的第一部分 用于对所述电子电路的预定义使用功能作出贡献，以及配置所述布线结构的第二部分，用于在向所述第二部分施加刺激信号时提供指示在所述电子电路中流动的电流的值的信息，其中至少一个 同时执行部分第一部分的配置和第二部分的配置。