公开(公告)号：US10564699B2

公开(公告)日：2020-02-18

申请号：US16223818

申请日：2018-12-18

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nadav Shulman ,  Alon Naveh ,  Hisham Abu-Salah

IPC: G06F12/00 ,  G06F1/3234 ,  G06F12/0864 ,  G06F12/084 ,  G06F1/28 ,  G06F12/0802 ,  G06F1/3287 ,  G06F12/0846

Abstract: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.

公开(公告)号：US20190317773A1

公开(公告)日：2019-10-17

申请号：US16388670

申请日：2019-04-18

Applicant: Intel Corporation

Inventor： Guy M. Therien ,  Paul S. Diefenbaugh ,  Anil Aggarwal ,  Andrew D. Henroid ,  Jeremy J. Shrall ,  Efraim Rotem ,  Krishnakanth V. Sistla ,  Eliezer Weissmann

IPC: G06F9/4401 ,  G06F16/22 ,  G06F1/324 ,  G06F1/3234 ,  G06F9/44 ,  G06F1/26 ,  G06F9/22 ,  G06F9/445 ,  G06F11/36 ,  G06F1/3203 ,  G06F11/34 ,  G06F11/30 ,  G06F1/3296 ,  G06F1/28

Abstract: The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system.

公开(公告)号：US10379596B2

公开(公告)日：2019-08-13

申请号：US15227040

申请日：2016-08-03

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Nir Rosenzweig ,  Efraim Rotem ,  Yoav Ben-Raphael ,  Alon Naveh

IPC: G06F1/3206 ,  G06F1/3287 ,  G06F1/3296

Abstract: In one embodiment, a processor includes: a plurality of cores; a power controller including a logic to autonomously demote a first request for at least one core of the plurality of cores to enter a first low power state, to cause the at least one core to enter a second low power state, the first low power state a deeper low power state than the second low power state; and an interface to receive an input from a system software, the input including at least one demotion control parameter, where the logic is to autonomously demote the first request based at least in part on the at least one demotion control parameter. Other embodiments are described and claimed.

公开(公告)号：US20190102229A1

公开(公告)日：2019-04-04

申请号：US15721858

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Monica Gupta ,  Russell J. Fenger ,  Vijay Dhanraj ,  Deepak Samuel Kirubakaran ,  Srividya Ambale ,  Israel Hirsh ,  Eliezer Weissmann ,  Hisham Abu-Salah

IPC: G06F9/50

Abstract: Technologies are provided in embodiments to dynamically bias performance of logical processors in a core of a processor. One embodiment includes identifying a first logical processor associated with a first thread of an application and a second logical processor associated with a second thread, obtaining first and second thread preference indicators associated with the first and second threads, respectively, computing a first relative performance bias value for the first logical processor based, at least in part, on a relativeness of the first and second thread preference indicators, and adjusting a performance bias of the first logical processor based on the first relative performance bias value. Embodiments can further include increasing the performance bias of the first logical processor based, at least in part, on the first relative performance bias value indicating a first performance preference that is higher than a second performance preference.

公开(公告)号：US20190102227A1

公开(公告)日：2019-04-04

申请号：US15720222

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Avinash Ananthakrishnan ,  Vijay Dhanraj ,  Russell Fenger ,  Vivek Garg ,  Eugene Gorbatov ,  Stephen Gunter ,  Monica Gupta ,  Efraim Rotem ,  Krishnakanth Sistla ,  Guy Therien ,  Ankush Verma ,  Eliezer Weissmann

IPC: G06F9/50 ,  G06F9/48

Abstract: In an embodiment, a processor includes a plurality of processing engines (PEs) to execute threads, and a guide unit. The guide unit is to: monitor execution characteristics of the plurality of PEs and the threads; generate a plurality of PE rankings, each PE ranking including the plurality of PEs in a particular order; and store the plurality of PE rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of PEs using the plurality of PE rankings. Other embodiments are described and claimed.

公开(公告)号：US10216246B2

公开(公告)日：2019-02-26

申请号：US15281651

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Doron Rajwan ,  Efraim Rotem ,  Eliezer Weissmann ,  Avinash N. Ananthakrishnan ,  Dorit Shapira

IPC: G06F1/32 ,  G06F9/50 ,  G06F1/3228 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3237 ,  G06F17/50 ,  G06F1/3234 ,  G06F1/3293

Abstract: In an embodiment, a processor includes processing cores, and a central control unit to: concurrently execute an outer control loop and an inner control loop, wherein the outer control loop is to monitor the processor as a whole, and wherein the inner control loop is to monitor a first processing core included in the processor; determine, based on the outer control loop, a first control action for the first processing core included in the processor; determine, based on the inner control loop, a second control action for the first processing core included in the processor; based on a comparison of the first control action and the second control action, select one of the first control action and the second control action as a selected control action; and apply the selected control action to the first processing core. Other embodiments are described and claimed.

公开(公告)号：US10007321B2

公开(公告)日：2018-06-26

申请号：US15426876

申请日：2017-02-07

Applicant: Intel Corporation

Inventor： Hisham Abu Salah ,  Eliezer Weissmann ,  Efraim Rotem ,  Paul S. Diefenbaugh ,  Jay D. Schwartz ,  Sharad C. Tripathi

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/3206 ,  G06F1/3293 ,  Y02D10/126

Abstract: Techniques described above may enhance the power-performance efficiency of a processor, SoC, or a computing system. Embodiments described here allow an increase in frequency of the clock signal to a peak frequency value in response to detecting an occurrence of a burst of high activity within the low processor utilization periods. A power management unit may accumulate the budget during the low or idle processor utilization periods and the level of activity of the burst of high activity signal may be determined. The PMU may increase the frequency of the clock signal provided to the processing cores if the level of the burst of high activity exceeds a first threshold value and an accumulated budget value exceeds a second threshold value.

公开(公告)号：US09760160B2

公开(公告)日：2017-09-12

申请号：US14722518

申请日：2015-05-27

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Efraim Rotem ,  Hisham Abu Salah ,  Yoni Aizik ,  Doron Rajwan ,  Nir Rosenzweig ,  Gal Leibovich ,  Yevgeni Sabin ,  Shay Levy

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/00 ,  G06F9/50

CPC classification number: G06F1/3287 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3296 ,  G06F9/5094 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/172

Abstract: In one embodiment, a processor comprises: a plurality of processing engines including a first processing engine and a second processing engine to independently execute instructions; and a power controller including a performance state control logic to control a performance state of at least one of the processing engines, and a first logic to determine an average number of active processing engines over a first window, an estimated activity level of the processor for the first window, and adjust at least one of a window length at which the performance state control logic is to perform a performance state determination and at least one activity level threshold, based at least in part on a comparison of the estimated activity level and the average number of active processing engines. Other embodiments are described and claimed.

公开(公告)号：US20170090945A1

公开(公告)日：2017-03-30

申请号：US14866584

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Doron Rajwan ,  Eliezer Weissmann ,  Yoni Aizik ,  Itai Feit ,  Tal Kuzi ,  Tomer Ziv ,  Nadav Shulman

IPC: G06F9/44 ,  G06F1/24

CPC classification number: G06F11/3024 ,  G01V11/002 ,  G06F1/3228 ,  G06F1/324 ,  G06F9/5094 ,  G06F11/3058 ,  G06F11/3409 ,  G06F11/3419 ,  G06F11/3452 ,  G06F11/348 ,  G06F2201/88

Abstract: Methods and apparatus relating to techniques for flexible and/or dynamic frequency-related telemetry are described. In an embodiment, logic, coupled to a processor, communicates information to a module. The communicated information includes a duration counter value corresponding to a duration in which an operating characteristic of the processor is controlled. Other embodiments are also disclosed and claimed.

公开(公告)号：US09348401B2

公开(公告)日：2016-05-24

申请号：US13926025

申请日：2013-06-25

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Efraim Rotem ,  Paul Diefenbaugh ,  Guy Therien ,  Nir Rosenzweig

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/3243 ,  G06F1/3293 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/152

Abstract: In an embodiment, a processor includes multiple cores each to independently execute instructions and a power control unit (PCU) coupled to the plurality of cores to control power consumption of the processor. The PCU may include a mapping logic to receive a performance scale value from an operating system (OS) and to calculate a dynamic performance-frequency mapping based at least in part on the performance scale value. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括各自独立地执行指令的多个核心以及耦合到多个核心的功率控制单元（PCU），以控制处理器的功率消耗。 PCU可以包括映射逻辑以从操作系统（OS）接收性能标度值，并且至少部分地基于性能标度值来计算动态性能 - 频率映射。 描述和要求保护其他实施例。