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公开(公告)号：US09262163B2
公开(公告)日：2016-02-16
申请号：US13730834
申请日：2012-12-29
Applicant: Intel Corporation
Inventor： Tsvika Kurts , Ofer Levy , Itamar Kazachinsky , Gabi Malka , Zeev Sperber , Jason W. Brandt
CPC classification number: G06F9/30145 , G06F11/00 , G06F11/3471 , G06F11/36 , G06F13/4068 , G06F2201/865
Abstract: A method of an aspect includes generating real time instruction trace (RTIT) packets for a first logical processor of a processor. The RTIT packets indicate a flow of software executed by the first logical processor. The RTIT packets are stored in an RTIT queue corresponding to the first logical processor. The RTIT packets are transferred from the RTIT queue to memory predominantly with firmware of the processor. Other methods, apparatus, and systems are also disclosed.
Abstract translation: 一方面的方法包括为处理器的第一逻辑处理器生成实时指令跟踪（RTIT）分组。 RTIT分组指示由第一逻辑处理器执行的软件的流程。 RTIT分组被存储在对应于第一逻辑处理器的RTIT队列中。 RTIT数据包主要通过处理器的固件从RTIT队列传送到存储器。 还公开了其它方法，装置和系统。
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公开(公告)号：US20230092268A1
公开(公告)日：2023-03-23
申请号：US17992407
申请日：2022-11-22
Applicant: Intel Corporation
Inventor： Michael W. Chynoweth , Jonathan D. Combs , Joseph K. Olivas , Beeman C. Strong , Rajshree A. Chabukswar , Ahmad Yasin , Jason W. Brandt , Ofer Levy , John M. Esper , Andreas Kleen , Christopher M. Chrulski
IPC: G06F9/30
Abstract: A processor includes a counter to store a cycle count that tracks a number of cycles between retirement of a first branch instruction and retirement of a second branch instruction during execution of a set of instructions. The processor further includes a stack of registers coupled to the counter, wherein the stack of registers is to store branch type information including: a first value of the counter when the first branch instruction is retired; a second value of the counter when the second branch instruction is retired; a first type information value indicating a type of the first branch instruction; and a second type information value indicating a type of the second branch instruction.
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公开(公告)号：US10152451B2
公开(公告)日：2018-12-11
申请号：US15490743
申请日：2017-04-18
Applicant: Intel Corporation
Inventor： Zeev Sperber , Robert Valentine , Shlomo Raikin , Stanislav Shwartsman , Gal Ofir , Igor Yanover , Guy Patkin , Ofer Levy
Abstract: Methods and apparatus are disclosed using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode scatter/gather instructions and generate micro-operations. An index array holds a set of indices and a corresponding set of mask elements. A finite state machine facilitates the scatter operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. Storage is allocated in a buffer for each of the set of addresses being generated. Data elements corresponding to the set of addresses being generated are copied to the buffer. Addresses from the set are accessed to store data elements if a corresponding mask element has said first value and the mask element is changed to a second value responsive to completion of their respective stores.
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公开(公告)号：US20180217839A1
公开(公告)日：2018-08-02
申请号：US15423143
申请日：2017-02-02
Applicant: INTEL CORPORATION
Inventor： Michael W. Chynoweth , Jonathan D. Combs , Joseph K. Olivas , Beeman C. Strong , Rajshree A. Chabukswar , Ahmad Yasin , Jason W. Brandt , Ofer Levy , John M. Esper , Andreas Kleen , Christopher M. Chrulski
CPC classification number: G06F9/3005
Abstract: An example processor that includes a decoder, an execution circuit, a counter, and a last branch recorder (LBR) register. The decoder may decode a branch instruction for a program. The execution circuit may be coupled to the decoder, where the execution circuit may execute the branch instruction. The counter may be coupled to the execution circuit, where the counter may store a cycle count. The LBR register coupled to the execution circuit, where the LBR register may include a counter field to store a first value of the counter when the branch instruction is executed and a type field to store type information indicating a type of the branch instruction.
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15.发明授权公开(公告)号：US09612938B2
公开(公告)日：2017-04-04
申请号：US13895595
申请日：2013-05-16
Applicant: Intel Corporation
Inventor： Frank Binns , Matthew C. Merten , Mayank Bomb , Beeman C. Strong , Peter Lachner , Jason W. Brandt , Itamar Kazachinsky , Ofer Levy , Md A. Rahman
CPC classification number: G06F11/3636 , G06F11/3024 , G06F11/3055 , G06F11/3476 , G06F11/348 , G06F2201/865
Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for providing status of a processing device with a periodic synchronization point in an instruction tracing system. For example, the method may include generating a boundary packet based on a unique byte pattern in a packet log. The boundary packet provides a starting point for packet decode. The method may also include generating a plurality of state packets based on status information of the processor. The plurality of state packets follows the boundary packet when outputted into the packet log.
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Patent Agency Ranking
公开(公告)号：US20160259646A1
公开(公告)日：2016-09-08
申请号：US15155204
申请日：2016-05-16
Applicant: Intel Corporation
Inventor： Ahmad Yasin , Michael W. Chynoweth , Ofer Levy , Jason W. Brandt , Angela Schmid
CPC classification number: G06F9/3806 , G06F9/30058 , G06F9/30098 , G06F11/3419 , G06F11/348 , G06F2201/865 , G06F2201/88
Abstract: A processing device implementing an elapsed cycle timer in last branch records (LBRs) is disclosed. A processing device of the disclosure includes a last branch record (LBR) counter to iterate with each cycle of the processing device. The processing device further includes at least one register communicably coupled to the LBR counter, the at least one register to provide an LBR structure comprising a plurality of LBR entries. An LBR entry of the plurality of LBR entries includes an address instruction pointer (IP) of a branch instruction executed by the processing device, an address IP of a target of the branch instruction, and an elapsed time field that stores a value of the LBR counter in response to creation of the LBR entry.
Abstract translation: 公开了一种在最后的分支记录（LBR）中实现经过周期定时器的处理装置。 本公开的处理装置包括与处理装置的每个周期重复的最后一个分支记录（LBR）计数器。 所述处理设备还包括至少一个可通信地耦合到所述LBR计数器的寄存器，所述至少一个寄存器提供包括多个LBR入口的LBR结构。 多个LBR条目的LBR条目包括由处理装置执行的分支指令的地址指令指针（IP），分支指令的目标的地址IP以及存储LBR的值的经过时间字段 反对创建LBR条目。
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公开(公告)号：US20160117171A1
公开(公告)日：2016-04-28
申请号：US14992658
申请日：2016-01-11
Applicant: INTEL CORPORATION
Inventor： Tsvika Kurts , Ofer Levy , Itamar Kazachinsky , Gabi Malka , Zeev Sperber , Jason W. Brandt
CPC classification number: G06F9/30145 , G06F11/00 , G06F11/3471 , G06F11/36 , G06F13/4068 , G06F2201/865
Abstract: A method of an aspect includes generating real time instruction trace (RTIT) packets for a first logical processor of a processor. The RTIT packets indicate a flow of software executed by the first logical processor. The RTIT packets are stored in an RTIT queue corresponding to the first logical processor. The RTIT packets are transferred from the RTIT queue to memory predominantly with firmware of the processor. Other methods, apparatus, and systems are also disclosed.
Abstract translation: 一方面的方法包括为处理器的第一逻辑处理器生成实时指令跟踪（RTIT）分组。 RTIT分组指示由第一逻辑处理器执行的软件的流程。 RTIT分组被存储在对应于第一逻辑处理器的RTIT队列中。 RTIT数据包主要通过处理器的固件从RTIT队列传送到存储器。 还公开了其它方法，装置和系统。
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公开(公告)号：US20200210178A1
公开(公告)日：2020-07-02
申请号：US16811242
申请日：2020-03-06
Applicant: Intel Corporation
Inventor： Michael W. Chynoweth , Jonathan D. Combs , Joseph K. Olivas , Beeman C. Strong , Rajshree A. Chabukswar , Ahmad Yasin , Jason W. Brandt , Ofer Levy , John M. Esper , Andreas Kleen , Christopher M. Chrulski
IPC: G06F9/30
Abstract: A processor includes a counter to store a cycle count that tracks a number of cycles between retirement of a first branch instruction and retirement of a second branch instruction during execution of a set of instructions. The processor further includes a stack of registers coupled to the counter, wherein the stack of registers is to store branch type information including: a first value of the counter when the first branch instruction is retired; a second value of the counter when the second branch instruction is retired; a first type information value indicating a type of the first branch instruction; and a second type information value indicating a type of the second branch instruction.
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公开(公告)号：US09716646B2
公开(公告)日：2017-07-25
申请号：US14334071
申请日：2014-07-17
Applicant: Intel Corporation
Inventor： Tsvika Kurts , Beeman C. Strong , Ofer Levy , Gabi Malka , Zeev Sperber
CPC classification number: H04L43/50 , H04J3/0664 , H04L43/106
Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for using thresholds to gate timing packet generation in a tracing system (TS). For example, the method may include generating and outputting a trace data (TD) packet into a packet log. The method also includes generating and outputting a timing packet (TM) corresponding to the TD packet into the packet log when a number of clock cycles elapsed since an output of a previous TM packet exceeds a clock threshold value.
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公开(公告)号：US09696997B2
公开(公告)日：2017-07-04
申请号：US14992658
申请日：2016-01-11
Applicant: INTEL CORPORATION
Inventor： Tsvika Kurts , Ofer Levy , Itamar Kazachinsky , Gabi Malka , Zeev Sperber , Jason W. Brandt
CPC classification number: G06F9/30145 , G06F11/00 , G06F11/3471 , G06F11/36 , G06F13/4068 , G06F2201/865
Abstract: A method of an aspect includes generating real time instruction trace (RTIT) packets for a first logical processor of a processor. The RTIT packets indicate a flow of software executed by the first logical processor. The RTIT packets are stored in an RTIT queue corresponding to the first logical processor. The RTIT packets are transferred from the RTIT queue to memory predominantly with firmware of the processor. Other methods, apparatus, and systems are also disclosed.
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