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    Composite core circuit module system and method
    14.
    发明申请
    Composite core circuit module system and method 有权
    复合核心电路模块系统及方法

    公开(公告)号：US20070176286A1

    公开(公告)日：2007-08-02

    申请号：US11345910

    申请日：2006-02-02

    Applicant: James Wehrly

    Inventor： James Wehrly

    IPC: H01L23/34

    CPC classification number: H05K1/141 ,  H01L25/0655 ,  H01L2924/0002 ,  H05K1/117 ,  H05K1/144 ,  H05K1/181 ,  H05K2201/042 ,  H05K2201/10159 ,  H05K2201/10189 ,  H05K2201/1056 ,  H05K2201/10734 ,  H05K2203/1572 ,  H01L2924/00

    Abstract: A circuit module is provided in which at least one secondary substrate and preferably two such secondary substrates are populated with integrated circuits (ICs). A rigid core substrate for the circuit module is comprised of a structural member and a connective member. In a preferred embodiment, the structural member is comprised of thermally conductive material while the connective member is comprised of conventional PWB material. The secondary substrate(s) are connected to the connective member with a variety of techniques and materials while, in a preferred embodiment, the connective member exhibits, in a preferred embodiment, traditional module contacts which provide an edge connector capability to allow the module to supplant traditional DIMMs.

    Abstract translation: 提供了一种电路模块，其中至少一个辅助衬底，优选地两个这样的辅助衬底填充有集成电路（IC）。 用于电路模块的刚性芯基板由结构构件和连接构件组成。 在优选实施例中，结构构件由导热材料构成，而连接构件由常规PWB材料构成。 第二基底通过各种技术和材料连接到连接构件，而在优选实施例中，在优选实施例中，连接构件表现出传统的模块触点，其提供边缘连接器能力以允许模块 取代传统DIMM。

    High density memory card system and method
    15.
    发明申请
    High density memory card system and method 有权
    高密度存储卡系统及方法

    公开(公告)号：US20070158802A1

    公开(公告)日：2007-07-12

    申请号：US11434964

    申请日：2006-05-16

    Applicant: James Wehrly

    Inventor： James Wehrly

    IPC: H01L23/02 ,  H01L21/48

    CPC classification number: H01L25/105 ,  G06K19/07732 ,  H01L23/5387 ,  H01L23/5388 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/0002 ,  H05K1/189 ,  H05K2201/10159 ,  H05K2201/10545 ,  H05K2201/10689 ,  H05K2201/2018 ,  H01L2924/00

    Abstract: The present invention provides a system and method for employing leaded packaged memory devices in memory cards. Leaded packaged ICs are disposed on one or both sides of a flex circuitry structure to create an IC-populated structure. In a preferred embodiment, leads of constituent leaded IC packages are configured to allow the lower surface of the leaded IC packages to contact respective surfaces of the flex circuitry structure. Contacts for typical embodiments are supported by a rigid portion of the flex circuitry structure and the IC-populated structure is disposed in a casing to provide card structure for the module.

    Abstract translation: 本发明提供了一种在存储卡中采用引线封装的存储器件的系统和方法。 引线封装IC布置在柔性电路结构的一侧或两侧以产生IC填充结构。 在优选实施例中，构成引线IC封装的引线被配置为允许引线IC封装的下表面接触柔性电路结构的相应表面。 用于典型实施例的触头由柔性电路结构的刚性部分支撑，并且IC填充结构设置在壳体中以为模块提供卡结构。

    Stacked module systems and methods
    16.
    发明申请
    Stacked module systems and methods 有权
    堆叠模块系统和方法

    公开(公告)号：US20060092614A1

    公开(公告)日：2006-05-04

    申请号：US11263627

    申请日：2005-10-31

    Applicant: Julian Partridge ,  James Wehrly ,  David Roper ,  Joseph Villani

    Inventor： Julian Partridge ,  James Wehrly ,  David Roper ,  Joseph Villani

    IPC: H05K7/12 ,  H01L23/02 ,  H05K7/10 ,  H01L23/52

    CPC classification number: H01L23/49833 ,  H01L23/5385 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06579 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H05K3/305 ,  H05K2201/056 ,  H05K2201/10734 ,  Y02P70/613 ,  H01L2224/0401

    Abstract: The present invention stacks integrated circuit packages into circuit modules. In a preferred embodiment, solder paste and primary adhesive respectively are applied to selected locations on the flex circuitry. Supplemental adhesive is applied to add ional locations on the flex circuitry, CSP, or other component. The flex circuitry and the CSP are brought into proximity with each other. During solder reflow operation, a force is applied and the CSP collapses toward the flex circuitry, displacing the primary adhesive and the supplemental adhesive. The supplemental adhesive establishes a bond providing additional support to the flex circuitry. In another embodiment, CSPs or other integrated circuit packages are bonded to each other or to other components with a combination of adhesives. A rapid bond adhesive maintains alignment of the bonded packages and/or components during assembly, and a structural bond adhesive provides additional strength and/or structural integrity to the bond.

    Abstract translation: 本发明将集成电路封装堆叠成电路模块。 在优选实施例中，焊膏和主粘合剂分别施加到柔性电路上的选定位置。 补充粘合剂应用于柔性电路，CSP或其他部件上的添加位置。 柔性电路和CSP彼此接近。 在回流焊接操作期间，施加力并且CSP朝向柔性电路折叠，使主粘合剂和补充粘合剂移位。 补充粘合剂建立了粘合，为柔性电路提供额外的支撑。 在另一个实施例中，CSP或其他集成电路封装通过粘合剂的组合彼此结合或连接到其它部件。 快速粘合粘合剂在组装期间保持粘合的包装和/或部件的对准，并且结构粘合粘合剂为粘合剂提供附加的强度和/或结构完整性。

    Adapted leaded integrated circuit module
    17.
    发明申请
    Adapted leaded integrated circuit module 审中-公开
    适应领先的集成电路模块

    公开(公告)号：US20060055024A1

    公开(公告)日：2006-03-16

    申请号：US10940074

    申请日：2004-09-14

    Applicant: James Wehrly

    Inventor： James Wehrly

    IPC: H01L23/48 ,  H01L23/34

    CPC classification number: H05K1/181 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/0002 ,  H05K2201/10515 ,  H05K2201/10689 ,  H05K2201/10924 ,  Y02P70/611 ,  H01L2924/00

    Abstract: An interposer is provided having an array of surface mount pads along the upper side and an array of BGA (ball grid array) contacts on the lower side. A module of one or more leaded packaged ICs (integrated circuits) is mounted to the array of surface mount pads. The one or more leaded packaged integrated circuits are thereby adapted for connection to a BGA footprint. Various alternative embodiments for stacking the leaded packaged ICs, controlling thermal performance, and interconnecting with the interposer are disclosed.

    Abstract translation: 提供了具有沿着上侧的表面安装焊盘阵列和下侧的BGA（球栅阵列）阵列的阵列的插入器。 一个或多个引线封装IC（集成电路）的模块被安装到表面安装焊盘阵列。 因此，一个或多个引线封装的集成电路适于连接到BGA封装。 公开了用于堆叠引线封装IC，控制热性能和与插入器互连的各种替代实施例。

    Memory expansion and integrated circuit stacking system and method
    19.
    发明申请
    Memory expansion and integrated circuit stacking system and method 有权
    内存扩展和集成电路堆叠系统及方法

    公开(公告)号：US20050057911A1

    公开(公告)日：2005-03-17

    申请号：US10804452

    申请日：2004-03-19

    Applicant: Russell Rapport ,  James Cady ,  James Wilder ,  David Roper ,  James Wehrly ,  Jeff Buchle

    Inventor： Russell Rapport ,  James Cady ,  James Wilder ,  David Roper ,  James Wehrly ,  Jeff Buchle

    IPC: H01L25/065 ,  H01L25/10 ,  H05K7/06 ,  H01L23/538

    CPC classification number: H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/107 ,  H01L2924/3011 ,  H01L2924/00012

    Abstract: The present invention stacks integrated circuits (ICs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance. In a preferred embodiment of the memory addressing system, a high speed switching system selects a data line associated with each level of a stacked module to reduce the loading effect upon data signals in memory access.

    Abstract translation: 本发明将集成电路（IC）堆叠成节省PWB或其他板表面积的模块。 在另一方面，本发明提供了一种较低电容存储器扩展寻址系统和方法，并且优选地具有本文提供的CSP堆叠模块。 在根据本发明的优选实施例中，形式标准提供了一种物理形式，其允许在广泛的CSP封装系列中发现的许多变化的封装尺寸在使用标准连接柔性电路设计时被有利地使用。 在优选实施例中，将设计形式标准，以便传热材料例如铜，以改善热性能。 在存储器寻址系统的优选实施例中，高速交换系统选择与堆叠模块的每个级别相关联的数据线，以减少对存储器访问中的数据信号的负载影响。

    Stacked module systems and methods
    20.
    发明申请
    Stacked module systems and methods 审中-公开
    堆叠模块系统和方法

    公开(公告)号：US20050056921A1

    公开(公告)日：2005-03-17

    申请号：US10845029

    申请日：2004-05-13

    Applicant: James Wehrly ,  James Cady ,  Julian Partridge ,  David Roper

    Inventor： James Wehrly ,  James Cady ,  Julian Partridge ,  David Roper

    IPC: H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H01L23/02

    CPC classification number: H01L25/105 ,  H01L23/3114 ,  H01L23/4985 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2225/107

    Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. The CSPs employed in stacked modules devised in accordance with the present invention are connected with flex circuitry. That flex circuitry may exhibit one or more conductive layers with preferred embodiments having two conductive layers. A form standard is disposed along the lower planar surface and extends laterally beyond the package of one or more CSPs in a stacked module. The form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be comprised of heat conductive material such as copper, for example.

    Abstract translation: 本发明将芯片级封装集成电路（CSP）堆叠成保存PWB或其他板表面积的模块。 根据本发明设计的堆叠模块中采用的CSP与柔性电路连接。 该柔性电路可以呈现一个或多个导电层，优选实施例具有两个导电层。 形式标准沿着下平面表面设置并横向延伸超过堆叠模块中的一个或多个CSP的包装。 形式标准提供了一种物理形式，允许在采用标准连接柔性电路设计时，在广泛的CSP封装系列中发现许多变化的封装尺寸。 在优选实施例中，形式标准例如由导热材料例如铜构成。

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