公开(公告)号：US20180159470A1

公开(公告)日：2018-06-07

申请号：US15831572

申请日：2017-12-05

Applicant: MaxLinear, Inc.

Inventor： Xuefeng Chen ,  Hosein Zareie

IPC: H03B1/04 ,  H03B5/32

CPC classification number: H03B1/04 ,  H03B5/32 ,  H03B5/362 ,  H03B5/364 ,  H03B2202/044 ,  H03B2202/05

Abstract: Systems and methods are provided for generating reference signals with high interference immunity. A signal source may generate reference signals having a particular reference frequency based on characteristics of the source of the reference signals, for use in driving at least one component in a system. One or more processing may then process the generated reference signals, based on particular frequency positions relative to the particular reference frequency and other operations and/or components of the system. The processing may include filtering at the particular frequency positions. The particular frequency positions may correspond to the harmonics positions of the particular reference frequency. The signal source may be a crystal oscillator.

公开(公告)号：US20180013442A1

公开(公告)日：2018-01-11

申请号：US15711177

申请日：2017-09-21

Applicant: Maxlinear, Inc.

Inventor： Eric Fogleman ,  Sheng Ye ,  Xuefeng Chen ,  Kok Lim Chan

IPC: H03M1/06 ,  H03M1/00

CPC classification number: H03M1/0617 ,  H03M1/001 ,  H03M1/069 ,  H03M1/125 ,  H03M1/46 ,  H03M1/462

Abstract: An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.

公开(公告)号：US20170346500A1

公开(公告)日：2017-11-30

申请号：US15674700

申请日：2017-08-11

Applicant: MaxLinear, Inc.

Inventor： Xuefeng Chen ,  Kok Lim Chan ,  Eric Fogleman ,  Sheng Ye

IPC: H03M1/38 ,  H03M1/06 ,  H03M1/12 ,  H03M1/46

CPC classification number: H03M1/38 ,  H03M1/06 ,  H03M1/0682 ,  H03M1/125 ,  H03M1/466

Abstract: A system for processing signals may be configured to detect occurrence of particular errors, comprising meta-stability events, during digital conversion to analog signals, and to handle any detected meta-stability event, such as by adjusting at least a portion of a corresponding digital output based on detection of the meta-stability event. The adjusting of the digital output may comprise setting at least the portion of the digital output, such as to one of a plurality of predefined digital values or patterns. The system may comprise a code generator for generating and/or outputting the predefined digital values or patterns. The system may comprise a selector for adaptively selecting, for portions of the digital output, between output of normal processing path and between predefined values or patterns.

公开(公告)号：US20180351543A1

公开(公告)日：2018-12-06

申请号：US16057499

申请日：2018-08-07

Applicant: Maxlinear, Inc.

Inventor： Yongjian Tang ,  Xuefeng Chen

IPC: H03K17/06 ,  H03K17/687

CPC classification number: H03K17/063 ,  H03K17/687 ,  H03K2217/0054

Abstract: Methods and systems for reliable bootstrapping switches may comprise sampling a received signal with a bootstrapping switch, where the bootstrapping switch comprises a switching metal-oxide semiconductor (MOS) transistor having a pull-down path coupled to a gate terminal of the switching MOS transistor, wherein: source terminals of both a diode-connected transistor and a second MOS transistor are coupled to the gate terminal of the switching MOS transistor; drain terminals of both the diode-connected transistor and the second MOS transistor are coupled to a source terminal of a third MOS transistor, the third MOS transistor coupled in series with a fourth MOS transistor; and a drain terminal of the fourth MOS transistor is coupled to ground. The third and fourth MOS transistors may be in series with the second MOS transistor. A gate terminal of the fourth transistor may be switched from ground to a supply voltage to activate the pull-down path.

公开(公告)号：US10097193B2

公开(公告)日：2018-10-09

申请号：US15812365

申请日：2017-11-14

Applicant: Maxlinear, Inc.

Inventor： Pawandeep Taluja ,  Mingrui Zhu ,  Xuefeng Chen ,  Anand Anandakumar ,  Sheng Ye ,  Timothy Gallagher

IPC: H03M1/06 ,  H04W56/00 ,  H03M1/50 ,  H03M1/12 ,  H03M1/10

Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.

公开(公告)号：US20170163277A1

公开(公告)日：2017-06-08

申请号：US15436088

申请日：2017-02-17

Applicant: Maxlinear, Inc.

Inventor： Pawandeep Taluja ,  Mingrui Zhu ,  Xuefeng Chen ,  Anand Anandakumar ,  Sheng Ye ,  Timothy Leo Gallagher

IPC: H03M1/06 ,  H04W56/00 ,  H03M1/50 ,  H03M1/12 ,  H03M1/10

CPC classification number: H03M1/0612 ,  H03M1/1009 ,  H03M1/1038 ,  H03M1/1215 ,  H03M1/50 ,  H04L7/0087 ,  H04L25/08 ,  H04W56/00

Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.

公开(公告)号：US09577655B2

公开(公告)日：2017-02-21

申请号：US14920699

申请日：2015-10-22

Applicant: Maxlinear, Inc.

Inventor： Pawandeep Taluja ,  Mingrui Zhu ,  Xuefeng Chen ,  Anand Anandakumar ,  Sheng Ye ,  Timothy Leo Gallagher

IPC: H03M1/06 ,  H03M1/50 ,  H03M1/10 ,  H03M1/12 ,  H04L7/00 ,  H04L25/08 ,  H04W56/00

CPC classification number: H03M1/0612 ,  H03M1/1009 ,  H03M1/1038 ,  H03M1/1215 ,  H03M1/50 ,  H04L7/0087 ,  H04L25/08 ,  H04W56/00

Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is aliased onto a desired signal by a timing offset in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal. A decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.

Abstract translation: 用于时间交织的模数转换器定时失配校准和补偿的方法和系统可以包括在芯片上接收模拟信号，使用时间交织的模数转换器（ADC）将模拟信号转换成数字信号， 并且通过估计期望的数字输出信号和阻塞信号之间的复数耦合系数，将在时间交错ADC中的定时偏移上的混叠在期望信号上的阻塞信号减少。 解相关算法可以包括对称自适应去相关算法。 所接收的模拟信号可以由芯片上的校准音发生器产生。 混叠信号可以与来自乘法器的输出信号相加。 复数耦合系数可以利用求和信号上的去相关算法来确定。 乘法器可以被配置为利用所确定的复耦合系数来消除阻塞信号。

公开(公告)号：US20160322985A1

公开(公告)日：2016-11-03

申请号：US15151042

申请日：2016-05-10

Applicant: MaxLinear, Inc.

Inventor： Xuefeng Chen ,  Kok Lim Chan ,  Eric Fogleman ,  Sheng Ye

IPC: H03M1/38 ,  H03M1/12 ,  H03M1/46 ,  H03M1/06

CPC classification number: H03M1/38 ,  H03M1/06 ,  H03M1/0682 ,  H03M1/125 ,  H03M1/466

Abstract: Systems and methods are provided for detecting meta-stability during processing of signals. A meta-stability detector may comprise a timing control circuit, a plurality of signal adjustment circuits, and a plurality of signal state circuits. The timing control circuit may measure comparison time for each conversion cycle during analog-to-digital conversions. Each signal adjustment circuit may apply a logical operation to one or more input signals to the signal adjustment circuit, and provide a corresponding output signal. Each signal state circuit may store state information relating to one or more input signals to the signal state circuit, for at least one processing cycle; and provide an output signal based on prior stored information. The plurality of signal state circuits, plurality of signal adjustment circuits, and the timing control circuit may be arranged to generate one or more control signals for controlling an analog-to-digital converter (ADC) during the analog-to-digital conversions

Abstract translation: 提供了用于在信号处理期间检测元稳定性的系统和方法。 元稳定性检测器可以包括定时控制电路，多个信号调整电路和多个信号状态电路。 定时控制电路可以测量模数转换期间每个转换周期的比较时间。 每个信号调整电路可以向信号调整电路的一个或多个输入信号施加逻辑运算，并提供对应的输出信号。 至少一个处理周期，每个信号状态电路可以将与一个或多个输入信号有关的状态信息存储到信号状态电路; 并基于先前存储的信息提供输出信号。 多个信号状态电路，多个信号调节电路和定时控制电路可以被布置为在模数转换期间产生用于控制模数转换器（ADC）的一个或多个控制信号

公开(公告)号：US20160006450A1

公开(公告)日：2016-01-07

申请号：US14812327

申请日：2015-07-29

Applicant: MaxLinear, Inc.

Inventor： Xuefeng Chen ,  Kok Lim Chan ,  Eric Fogleman ,  Sheng Ye

IPC: H03M1/38 ,  H03M1/12 ,  H03M1/46 ,  H03M1/06

CPC classification number: H03M1/38 ,  H03M1/06 ,  H03M1/0682 ,  H03M1/125 ,  H03M1/466

Abstract: Methods and systems are provided for controlling signal processing outputs. In signal processing circuitry, searching through a plurality of quantization levels for a quantization level that matches an analog input, and when the search fails within a particular amount of time, adjusting at least a portion of an output of the signal processing circuitry. The adjusting comprises setting the at least portion of the output to a predefined value. Setting the output, or portions thereof, may comprise selecting between output of a normal processing path and output of a code generation path configured for handling search failures. Timing information may be generated for use in controlling generating of the output of the signal processing circuitry. The timing information may be used in measuring per-cycle operation time during the search through the plurality of quantization levels.

Abstract translation: 提供了用于控制信号处理输出的方法和系统。 在信号处理电路中，通过多个量化级别搜索与模拟输入匹配的量化级别，以及当在特定时间量内搜索失败时，调整信号处理电路的输出的至少一部分。 调整包括将输出的至少部分设置为预定值。 设置输出或其部分可以包括在正常处理路径的输出和被配置用于处理搜索失败的代码生成路径的输出之间进行选择。 可以产生用于控制信号处理电路的输出的产生的定时信息。 定时信息可以用于在通过多个量化级别的搜索期间测量每周期操作时间。

公开(公告)号：US09124291B2

公开(公告)日：2015-09-01

申请号：US13945579

申请日：2013-07-18

Applicant: MaxLinear, Inc.

Inventor： Xuefeng Chen ,  Kok Lim Chan ,  Eric Fogleman ,  Sheng Ye

IPC: H03M1/10 ,  H03M1/38 ,  H03M1/12 ,  H03M1/06 ,  H03M1/46

CPC classification number: H03M1/38 ,  H03M1/06 ,  H03M1/0682 ,  H03M1/125 ,  H03M1/466

Abstract: A system for processing signals may be configured to detect occurrence of particular errors, comprising meta-stability events, during digital conversion to analog signals, and to handle any detected meta-stability event, such as by adjusting at least a portion of a corresponding digital output based on detection of the meta-stability event. The adjusting of the digital output may comprise setting at least the portion of the digital output, such as to one of a plurality of predefined digital values or patterns. The system may comprise a code generator for generating and/or outputting the predefined digital values or patterns. The system may comprise a selector for adaptively selecting, for portions of the digital output, between output of normal processing path and between predefined values or patterns.

Abstract translation: 用于处理信号的系统可以被配置为在数字转换到模拟信号期间检测包括元稳定性事件的特定错误的发生，并且处理任何检测到的元稳定性事件，例如通过调整相应数字的至少一部分 基于元稳定事件检测的输出。 数字输出的调整可以包括至少设置数字输出的一部分，诸如多个预定数字值或模式之一。 系统可以包括用于生成和/或输出预定数字值或码型的码发生器。 系统可以包括选择器，用于针对数字输出的部分，在正常处理路径的输出之间和预定义的值或模式之间自适应地选择。