公开(公告)号：US09547602B2

公开(公告)日：2017-01-17

申请号：US13831176

申请日：2013-03-14

Applicant: NVIDIA Corporation

Inventor： Alexander Klaiber ,  Guillermo Juan Rozas

IPC: G06F12/00 ,  G06F12/08 ,  G06F12/10

CPC classification number: G06F12/0891 ,  G06F12/0862 ,  G06F12/1027

Abstract: Presented systems and methods can facilitate efficient information storage and tracking operations, including translation look aside buffer operations. In one embodiment, the systems and methods effectively allow the caching of invalid entries (with the attendant benefits e.g., regarding power, resource usage, stalls, etc), while maintaining the illusion that the TLBs do not in fact cache invalid entries (e.g., act in compliance with architectural rules). In one exemplary implementation, an “unreal” TLB entry effectively serves as a hint that the linear address in question currently has no valid mapping. In one exemplary implementation, speculative operations that hit an unreal entry are discarded; architectural operations that hit an unreal entry discard the entry and perform a normal page walk, either obtaining a valid entry, or raising an architectural fault.

Abstract translation: 提出的系统和方法可以促进有效的信息存储和跟踪操作，包括翻译旁边的缓冲操作。 在一个实施例中，系统和方法有效地允许无效条目的缓存（伴随的优点，例如关于功率，资源使用，停顿等），同时保持TLB实际上不高速缓存无效条目的错觉（例如， 按照建筑规则行事）。 在一个示例性实现中，“虚幻”TLB条目有效地用作当前所讨论的线性地址没有有效映射的提示。 在一个示例性实施方式中，命中不真实条目的推测操作被丢弃; 命中虚幻条目的架构操作会丢弃该条目并执行正常的页面散步，获取有效的条目或提升架构故障。

公开(公告)号：US20140281392A1

公开(公告)日：2014-09-18

申请号：US13828865

申请日：2013-03-14

Applicant: NVIDIA CORPORATION

Inventor： Nathan Tuck ,  Alexander Klaiber ,  Ross Segelken ,  David Dunn ,  Ben Hertzberg ,  Rupert Brauch ,  Thomas Kistler ,  Guillermo J. Rozas ,  Madhu Swarna

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/3808 ,  G06F11/3466 ,  G06F11/3471 ,  G06F2201/81 ,  G06F2201/86 ,  G06F2201/865 ,  G06F2201/88

Abstract: The disclosure provides a micro-processing system operable in a hardware decoder mode and in a translation mode. In the hardware decoder mode, the hardware decoder receives and decodes non-native ISA instructions into native instructions for execution in a processing pipeline. In the translation mode, native translations of non-native ISA instructions are executed in the processing pipeline without using the hardware decoder. The system includes a code portion profile stored in hardware that changes dynamically in response to use of the hardware decoder to execute portions of non-native ISA code. The code portion profile is then used to dynamically form new native translations executable in the translation mode.

Abstract translation: 本公开提供了一种以硬件解码器模式和翻译模式操作的微处理系统。 在硬件解码器模式下，硬件解码器将非本地ISA指令接收并解码为本地指令，以便在处理流水线中执行。 在翻译模式中，非本地ISA指令的本地翻译在处理流水线中执行，而不使用硬件解码器。 系统包括存储在硬件中的代码部分简档，其响应于使用硬件解码器来动态地改变以执行非本地ISA代码的部分。 然后，代码部分简档用于动态地形成在翻译模式中可执行的新的本地翻译。

公开(公告)号：US20140164736A1

公开(公告)日：2014-06-12

申请号：US13708645

申请日：2012-12-07

Applicant: NVIDIA CORPORATION

Inventor： Guillermo J. Rozas ,  Alexander Klaiber ,  James van Zoeren ,  Paul Serris ,  Brad Hoyt ,  Sridharan Ramakrishnan ,  Hens Vanderschoot ,  Ross Segelken ,  Darrell D. Boggs ,  Magnus Ekman

IPC: G06F15/78

CPC classification number: G06F11/0721 ,  G06F9/30087 ,  G06F9/30181 ,  G06F9/3842 ,  G06F9/3851 ,  G06F11/0793 ,  G06F15/78

Abstract: Embodiments related to managing lazy runahead operations at a microprocessor are disclosed. For example, an embodiment of a method for operating a microprocessor described herein includes identifying a primary condition that triggers an unresolved state of the microprocessor. The example method also includes identifying a forcing condition that compels resolution of the unresolved state. The example method also includes, in response to identification of the forcing condition, causing the microprocessor to enter a runahead mode.

Abstract translation: 公开了在微处理器上管理懒惰跑道操作的实施例。 例如，本文描述的用于操作微处理器的方法的实施例包括识别触发微处理器的未解决状态的主要条件。 示例性方法还包括识别强制解决未解决状态的强制条件。 响应于强制条件的识别，示例性方法还包括使微处理器进入跑道模式。