公开(公告)号：US10108424B2

公开(公告)日：2018-10-23

申请号：US13828865

申请日：2013-03-14

Applicant: NVIDIA Corporation

Inventor： Nathan Tuck ,  Alexander Klaiber ,  Ross Segelken ,  David Dunn ,  Ben Hertzberg ,  Rupert Brauch ,  Thomas Kistler ,  Guillermo J. Rozas ,  Madhu Swarna

IPC: G06F9/30 ,  G06F9/38 ,  G06F11/34

Abstract: The disclosure provides a micro-processing system operable in a hardware decoder mode and in a translation mode. In the hardware decoder mode, the hardware decoder receives and decodes non-native ISA instructions into native instructions for execution in a processing pipeline. In the translation mode, native translations of non-native ISA instructions are executed in the processing pipeline without using the hardware decoder. The system includes a code portion profile stored in hardware that changes dynamically in response to use of the hardware decoder to execute portions of non-native ISA code. The code portion profile is then used to dynamically form new native translations executable in the translation mode.

公开(公告)号：US20140281392A1

公开(公告)日：2014-09-18

申请号：US13828865

申请日：2013-03-14

Applicant: NVIDIA CORPORATION

Inventor： Nathan Tuck ,  Alexander Klaiber ,  Ross Segelken ,  David Dunn ,  Ben Hertzberg ,  Rupert Brauch ,  Thomas Kistler ,  Guillermo J. Rozas ,  Madhu Swarna

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/3808 ,  G06F11/3466 ,  G06F11/3471 ,  G06F2201/81 ,  G06F2201/86 ,  G06F2201/865 ,  G06F2201/88

Abstract: The disclosure provides a micro-processing system operable in a hardware decoder mode and in a translation mode. In the hardware decoder mode, the hardware decoder receives and decodes non-native ISA instructions into native instructions for execution in a processing pipeline. In the translation mode, native translations of non-native ISA instructions are executed in the processing pipeline without using the hardware decoder. The system includes a code portion profile stored in hardware that changes dynamically in response to use of the hardware decoder to execute portions of non-native ISA code. The code portion profile is then used to dynamically form new native translations executable in the translation mode.

Abstract translation: 本公开提供了一种以硬件解码器模式和翻译模式操作的微处理系统。 在硬件解码器模式下，硬件解码器将非本地ISA指令接收并解码为本地指令，以便在处理流水线中执行。 在翻译模式中，非本地ISA指令的本地翻译在处理流水线中执行，而不使用硬件解码器。 系统包括存储在硬件中的代码部分简档，其响应于使用硬件解码器来动态地改变以执行非本地ISA代码的部分。 然后，代码部分简档用于动态地形成在翻译模式中可执行的新的本地翻译。