公开(公告)号：US10324725B2

公开(公告)日：2019-06-18

申请号：US15915975

申请日：2018-03-08

Applicant: Nvidia Corporation

Inventor： Nathan Tuck ,  David Dunn ,  Ross Segelken ,  Madhu Swarna

IPC: G06F9/30 ,  G06F11/07

Abstract: The disclosure provides a method and a system for identifying and replacing code translations that generate spurious fault events. In one embodiment the method includes executing a first set and a second set of native instructions, performing a third translation of a target instruction to form a third set of native instructions in response to a determination that a fault occurrence is attributed to a first translation, wherein the third set of native instructions is not the same as the second set of native instructions, and the third set of native instructions is not the same as the first set of native instructions, and executing the third set of native instructions.

公开(公告)号：US10108424B2

公开(公告)日：2018-10-23

申请号：US13828865

申请日：2013-03-14

Applicant: NVIDIA Corporation

Inventor： Nathan Tuck ,  Alexander Klaiber ,  Ross Segelken ,  David Dunn ,  Ben Hertzberg ,  Rupert Brauch ,  Thomas Kistler ,  Guillermo J. Rozas ,  Madhu Swarna

IPC: G06F9/30 ,  G06F9/38 ,  G06F11/34

Abstract: The disclosure provides a micro-processing system operable in a hardware decoder mode and in a translation mode. In the hardware decoder mode, the hardware decoder receives and decodes non-native ISA instructions into native instructions for execution in a processing pipeline. In the translation mode, native translations of non-native ISA instructions are executed in the processing pipeline without using the hardware decoder. The system includes a code portion profile stored in hardware that changes dynamically in response to use of the hardware decoder to execute portions of non-native ISA code. The code portion profile is then used to dynamically form new native translations executable in the translation mode.

公开(公告)号：US20180260222A1

公开(公告)日：2018-09-13

申请号：US15915975

申请日：2018-03-08

Applicant: Nvidia Corporation

Inventor： Nathan Tuck ,  David Dunn ,  Ross Segelken ,  Madhu Swarna

IPC: G06F9/30 ,  G06F11/07

CPC classification number: G06F9/3017 ,  G06F11/0721 ,  G06F11/0793

Abstract: The disclosure provides a method and a system for identifying and replacing code translations that generate spurious fault events. In one embodiment the method includes executing a first set and a second set of native instructions, performing a third translation of a target instruction to form a third set of native instructions in response to a determination that a fault occurrence is attributed to a first translation, wherein the third set of native instructions is not the same as the second set of native instructions, and the third set of native instructions is not the same as the first set of native instructions, and executing the third set of native instructions.

公开(公告)号：US20140281392A1

公开(公告)日：2014-09-18

申请号：US13828865

申请日：2013-03-14

Applicant: NVIDIA CORPORATION

Inventor： Nathan Tuck ,  Alexander Klaiber ,  Ross Segelken ,  David Dunn ,  Ben Hertzberg ,  Rupert Brauch ,  Thomas Kistler ,  Guillermo J. Rozas ,  Madhu Swarna

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/3808 ,  G06F11/3466 ,  G06F11/3471 ,  G06F2201/81 ,  G06F2201/86 ,  G06F2201/865 ,  G06F2201/88

Abstract: The disclosure provides a micro-processing system operable in a hardware decoder mode and in a translation mode. In the hardware decoder mode, the hardware decoder receives and decodes non-native ISA instructions into native instructions for execution in a processing pipeline. In the translation mode, native translations of non-native ISA instructions are executed in the processing pipeline without using the hardware decoder. The system includes a code portion profile stored in hardware that changes dynamically in response to use of the hardware decoder to execute portions of non-native ISA code. The code portion profile is then used to dynamically form new native translations executable in the translation mode.

Abstract translation: 本公开提供了一种以硬件解码器模式和翻译模式操作的微处理系统。 在硬件解码器模式下，硬件解码器将非本地ISA指令接收并解码为本地指令，以便在处理流水线中执行。 在翻译模式中，非本地ISA指令的本地翻译在处理流水线中执行，而不使用硬件解码器。 系统包括存储在硬件中的代码部分简档，其响应于使用硬件解码器来动态地改变以执行非本地ISA代码的部分。 然后，代码部分简档用于动态地形成在翻译模式中可执行的新的本地翻译。

公开(公告)号：US20140189310A1

公开(公告)日：2014-07-03

申请号：US13728669

申请日：2012-12-27

Applicant: NVIDIA CORPORATION

Inventor： Nathan Tuck ,  David Dunn ,  Ross Segelken ,  Madhu Swarna

IPC: G06F9/30

CPC classification number: G06F9/3017 ,  G06F11/0721 ,  G06F11/0793

Abstract: In one embodiment, a method for identifying and replacing code translations that generate spurious fault events includes detecting, while executing a first native translation of target instruction set architecture (ISA) instructions, occurrence of a fault event, executing the target ISA instructions or a functionally equivalent version thereof, determining whether occurrence of the fault event is replicated while executing the target ISA instructions or the functionally equivalent version thereof, and in response to determining that the fault event is not replicated, determining whether to allow future execution of the first native translation or to prevent such future execution in favor of forming and executing one or more alternate native translations.

Abstract translation: 在一个实施例中，用于识别和替换产生虚假故障事件的代码转换的方法包括：在执行目标指令集架构（ISA）指令的第一本机转换时，检测故障事件的发生，执行目标ISA指令或功能性 确定是否在执行目标ISA指令或其功能上等价的版本的同时复制故障事件的发生，并且响应于确定故障事件不被复制，确定是否允许将来执行第一本机平移 或者为了防止这种未来的执行，有利于形成和执行一个或多个替代的本地翻译。