公开(公告)号：US10289469B2

公开(公告)日：2019-05-14

申请号：US15338247

申请日：2016-10-28

Applicant: NVIDIA CORPORATION

Inventor： Nick Fortino ,  Fred Gruner ,  Ben Hertzberg

IPC: G06F11/00 ,  G06F11/07 ,  G06F9/30 ,  G06F9/38 ,  G06F11/36

Abstract: Systems and methods for enhancing reliability are presented. In one embodiment, a system comprises a processor configured to execute program instructions and contemporaneously perform reliability enhancement operations (e.g., fault checking, error mitigation, etc.) incident to executing the program instructions. The fault checking can include: identifying functionality of a particular portion of the program instructions; speculatively executing multiple sets of operations contemporaneously; and comparing execution results from the multiple sets of operations. The multiple sets of operations are functional duplicates of the particular portion of the program instructions. If the execution results have a matching value, then the value can be made architecturally visible. If the execution results do not have a matching value, the system can be put in a safe mode. An error mitigation operation can be performed can include a corrective procedure. The corrective procedure can include rollback to a known valid state.

公开(公告)号：US09552208B2

公开(公告)日：2017-01-24

申请号：US14137842

申请日：2013-12-20

Applicant: NVIDIA Corporation

Inventor： Ben Hertzberg ,  Guillermo Juan Rozas ,  Alexander Christian Klaiber ,  Nickolas Andrew Fortino

IPC: G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30189 ,  G06F9/30109 ,  G06F9/384

Abstract: A system, method, and computer program product are provided for remapping registers based on a change in execution mode. A sequence of instructions is received for execution by a processor and a change in an execution mode from a first execution mode to a second execution mode within the sequence of instructions is identified, where a first register mapping is associated with the first execution mode and a second register mapping is associated with the second execution mode. Data stored in a set of registers within a processor is reorganized based on the first register mapping and the second register mapping in response to the change in the execution mode.

Abstract translation: 提供了一种基于执行模式改变的重新映射寄存器的系统，方法和计算机程序产品。 接收指令序列以供处理器执行，并且识别在指令序列内的从第一执行模式到第二执行模式的执行模式的改变，其中第一寄存器映射与第一执行模式相关联， 第二寄存器映射与第二执行模式相关联。 基于第一寄存器映射和响应于执行模式的改变的第二寄存器映射，重新组织存储在处理器内的一组寄存器中的数据。

公开(公告)号：US10108424B2

公开(公告)日：2018-10-23

申请号：US13828865

申请日：2013-03-14

Applicant: NVIDIA Corporation

Inventor： Nathan Tuck ,  Alexander Klaiber ,  Ross Segelken ,  David Dunn ,  Ben Hertzberg ,  Rupert Brauch ,  Thomas Kistler ,  Guillermo J. Rozas ,  Madhu Swarna

IPC: G06F9/30 ,  G06F9/38 ,  G06F11/34

Abstract: The disclosure provides a micro-processing system operable in a hardware decoder mode and in a translation mode. In the hardware decoder mode, the hardware decoder receives and decodes non-native ISA instructions into native instructions for execution in a processing pipeline. In the translation mode, native translations of non-native ISA instructions are executed in the processing pipeline without using the hardware decoder. The system includes a code portion profile stored in hardware that changes dynamically in response to use of the hardware decoder to execute portions of non-native ISA code. The code portion profile is then used to dynamically form new native translations executable in the translation mode.

公开(公告)号：US20140281392A1

公开(公告)日：2014-09-18

申请号：US13828865

申请日：2013-03-14

Applicant: NVIDIA CORPORATION

Inventor： Nathan Tuck ,  Alexander Klaiber ,  Ross Segelken ,  David Dunn ,  Ben Hertzberg ,  Rupert Brauch ,  Thomas Kistler ,  Guillermo J. Rozas ,  Madhu Swarna

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/3808 ,  G06F11/3466 ,  G06F11/3471 ,  G06F2201/81 ,  G06F2201/86 ,  G06F2201/865 ,  G06F2201/88

Abstract: The disclosure provides a micro-processing system operable in a hardware decoder mode and in a translation mode. In the hardware decoder mode, the hardware decoder receives and decodes non-native ISA instructions into native instructions for execution in a processing pipeline. In the translation mode, native translations of non-native ISA instructions are executed in the processing pipeline without using the hardware decoder. The system includes a code portion profile stored in hardware that changes dynamically in response to use of the hardware decoder to execute portions of non-native ISA code. The code portion profile is then used to dynamically form new native translations executable in the translation mode.

Abstract translation: 本公开提供了一种以硬件解码器模式和翻译模式操作的微处理系统。 在硬件解码器模式下，硬件解码器将非本地ISA指令接收并解码为本地指令，以便在处理流水线中执行。 在翻译模式中，非本地ISA指令的本地翻译在处理流水线中执行，而不使用硬件解码器。 系统包括存储在硬件中的代码部分简档，其响应于使用硬件解码器来动态地改变以执行非本地ISA代码的部分。 然后，代码部分简档用于动态地形成在翻译模式中可执行的新的本地翻译。

公开(公告)号：US20180121273A1

公开(公告)日：2018-05-03

申请号：US15338247

申请日：2016-10-28

Applicant: NVIDIA CORPORATION

Inventor： Nick Fortino ,  Fred Gruner ,  Ben Hertzberg

IPC: G06F11/07 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F11/079 ,  G06F9/30174 ,  G06F9/3842 ,  G06F9/3859 ,  G06F9/3863 ,  G06F11/0721 ,  G06F11/0751 ,  G06F11/0793 ,  G06F11/36

Abstract: Systems and methods for enhancing reliability are presented. In one embodiment, a system comprises a processor configured to execute program instructions and contemporaneously perform reliability enhancement operations (e.g., fault checking, error mitigation, etc.) incident to executing the program instructions. The fault checking can include: identifying functionality of a particular portion of the program instructions; speculatively executing multiple sets of operations contemporaneously; and comparing execution results from the multiple sets of operations. The multiple sets of operations are functional duplicates of the particular portion of the program instructions. If the execution results have a matching value, then the value can be made architecturally visible. If the execution results do not have a matching value, the system can be put in a safe mode. An error mitigation operation can be performed can include a corrective procedure. The corrective procedure can include rollback to a known valid state.

公开(公告)号：US20150178085A1

公开(公告)日：2015-06-25

申请号：US14137842

申请日：2013-12-20

Applicant: NVIDIA Corporation

Inventor： Ben Hertzberg ,  Guillermo Juan Rozas ,  Alexander Christian Klaiber ,  Nickolas Andrew Fortino

IPC: G06F9/30

CPC classification number: G06F9/30189 ,  G06F9/30109 ,  G06F9/384

Abstract: A system, method, and computer program product are provided for remapping registers based on a change in execution mode. A sequence of instructions is received for execution by a processor and a change in an execution mode from a first execution mode to a second execution mode within the sequence of instructions is identified, where a first register mapping is associated with the first execution mode and a second register mapping is associated with the second execution mode. Data stored in a set of registers within a processor is reorganized based on the first register mapping and the second register mapping in response to the change in the execution mode.

Abstract translation: 提供了一种基于执行模式改变的重新映射寄存器的系统，方法和计算机程序产品。 接收指令序列以供处理器执行，并且识别在指令序列内的从第一执行模式到第二执行模式的执行模式的改变，其中第一寄存器映射与第一执行模式相关联， 第二寄存器映射与第二执行模式相关联。 基于第一寄存器映射和响应于执行模式的改变的第二寄存器映射，重新组织存储在处理器内的一组寄存器中的数据。