公开(公告)号：US20230269119A1

公开(公告)日：2023-08-24

申请号：US18182245

申请日：2023-03-10

Applicant: NVIDIA Corp.

Inventor： Sanquan Song ,  John Poulton

IPC: H04L25/49 ,  H04B1/00

CPC classification number: H04L25/4917 ,  H04B1/0082

Abstract: A transceiver circuit includes a receiver front end utilizing a ring oscillator, and a transmitter front end utilizing a pass-gate circuit in a first feedback path across a last-stage driver circuit. The transceiver circuit provides low impedance at low frequency and high impedance at high frequency, and desirable peaking behavior.

公开(公告)号：US20220353115A1

公开(公告)日：2022-11-03

申请号：US17243035

申请日：2021-04-28

Applicant: NVIDIA Corp.

Inventor： Sanquan Song ,  John Poulton

IPC: H04L25/49 ,  H04B1/00

Abstract: A transceiver circuit includes a receiver front end utilizing a ring oscillator, and a transmitter front end utilizing a pass-gate circuit in a first feedback path across a last-stage driver circuit. The transceiver circuit provides low impedance at low frequency and high impedance at high frequency, and desirable peaking behavior.

公开(公告)号：US10566958B1

公开(公告)日：2020-02-18

申请号：US16248558

申请日：2019-01-15

Applicant: NVIDIA Corp.

Inventor： Sanquan Song ,  Olakanmi Oluwole ,  John Poulton ,  Carl Thomas Gray

IPC: H03L7/099 ,  H03B27/00 ,  H03B1/04 ,  H03K3/012 ,  G06F1/06 ,  G06F1/10 ,  H03K3/03

Abstract: Injection locked oscillation circuits are applied along clock distribution circuit paths to increase clock signal bandwidth, reduce duty cycle error, reduce quadrature phase error, reduce clock signal jitter, and reduce clock signal power consumption.

公开(公告)号：US20240030916A1

公开(公告)日：2024-01-25

申请号：US17932052

申请日：2022-09-14

Applicant: NVIDIA Corp.

Inventor： Walker Joseph Turner ,  John Poulton ,  Sanquan Song

IPC: H03K19/0185 ,  H03K19/00

CPC classification number: H03K19/018521 ,  H03K19/0013 ,  H03K3/356165

Abstract: A level-shifting circuits utilizing storage cells for shifting signals low-to-high or high-to-low include control drivers with moving supply voltages. The moving supply voltages may power positive or negative supply terminals of the control drivers. The control drivers drive gates of common-source configured devices coupled to storage nodes of the storage cell.

公开(公告)号：US11133794B1

公开(公告)日：2021-09-28

申请号：US17020556

申请日：2020-09-14

Applicant: NVIDIA Corp.

Inventor： Stephen G Tell ,  Matthew Rudolph Fojtik ,  John Poulton

IPC: H03K5/14 ,  G04F10/00

Abstract: This disclosure relates to a circuit comprising a first, second, and third data latch, and an input for a data signal. The first data latch may be configured to sample a delayed version of the data signal in response to a first control signal. The second data latch may be configured to sample the delayed version of the data signal in response to a run clock signal. The run clock signal may be configured to run for a predefined number of clock cycles subsequent to the first control signal. The third data latch may be configured to sample either an output signal of the first data latch or an output signal of the second data latch in response to a second control signal received after the predefined number of clock cycles of the run clock signal.