公开(公告)号：US20100193227A1

公开(公告)日：2010-08-05

申请号：US12758908

申请日：2010-04-13

Applicant: Takashi KARIYA ,  Akira Mochida

Inventor： Takashi KARIYA ,  Akira Mochida

IPC: H05K1/16 ,  H05K1/00

CPC classification number: H01L21/6835 ,  H01L21/4857 ,  H01L2221/68345 ,  H01L2221/68363 ,  H01L2224/05001 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/0102 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H05K1/162 ,  H05K3/4602 ,  H05K2201/0175 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09718 ,  H05K2203/0353 ,  Y10T29/435 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A printed wiring board including a first insulating layer, a second insulating layer formed over the first insulating layer, a capacitor portion including an upper electrode, a lower electrode and a ceramic high dielectric layer formed between the upper electrode and the lower electrode, the capacitor portion sandwiched by the first insulating layer and the second insulating layer, an upper electrode connecting portion passing through the capacitor portion without contact and through the second insulating layer and electrically connected to the upper electrode of the capacitor portion, and a lower electrode connecting portion passing through the second insulating layer and the upper electrode of the capacitor portion without contact and electrically connected to the lower electrode in contact.

Abstract translation: 一种印刷布线板，包括形成在第一绝缘层上的第一绝缘层，第二绝缘层，形成在上电极和下电极之间的上电极，下电极和陶瓷高介电层的电容器部分，电容器 夹在第一绝缘层和第二绝缘层之间的部分，通过电容器部分而没有接触并穿过第二绝缘层并电连接到电容器部分的上电极的上电极连接部分和通过电容器部分的下电极连接部分 通过第二绝缘层和电容器部分的上电极而不接触并与下电极接触地电连接。

公开(公告)号：US20100064512A1

公开(公告)日：2010-03-18

申请号：US12608568

申请日：2009-10-29

Applicant: Takashi KARIYA ,  Hironori Tanaka

Inventor： Takashi KARIYA ,  Hironori Tanaka

IPC: H05K3/30 ,  H05K3/10

CPC classification number: H05K1/18 ,  H01L24/16 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01025 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/113 ,  H05K1/162 ,  H05K3/4602 ,  H05K3/4652 ,  H05K7/00 ,  H05K2201/0175 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/10674 ,  Y10T29/49133 ,  Y10T29/49162 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A multilayer printed wiring board includes a mounting portion supporting a semiconductor device and a layered capacitor portion including first and second layered electrodes and a ceramic high-dielectric layer therebetween. The first layered electrode is connected to a ground line and the second layered electrode is connected to a power supply line. The ratio of number of via holes, each constituting a conducting path part electrically connecting a ground pad to the ground line of a wiring pattern and passing through the second layered electrode in non-contact, to number of ground pads is 0.05 to 0.7. The ratio of number of second rod-shaped conductors, each constituting a conducting path part electrically connecting a power supply pad to the power supply line of the wiring pattern and passing through the first layered electrode in non-contact, to number of power supply pad is 0.05 to 0.7.

Abstract translation: 多层印刷布线板包括支撑半导体器件的安装部分和包括第一和第二层状电极的层状电容器部分和其间的陶瓷高介电层。 第一层状电极连接到地线，第二层状电极连接到电源线。 构成将接地焊盘与布线图案的接地线电连接并且非接触地穿过第二层状电极的导电路径部分的通孔数量的比率与接地焊盘数目的比为0.05〜0.7。 第二棒状导体的数量比构成将电源焊盘与布线图案的电源线电连接并且非接触地穿过第一层状电极的导电路径部分的数量与供电焊盘的数量 为0.05〜0.7。

公开(公告)号：US20100031503A1

公开(公告)日：2010-02-11

申请号：US12572000

申请日：2009-10-01

Applicant: Hajime SAKAMOTO ,  Tadashi SUGIYAMA ,  Dongdong WANG ,  Takashi KARIYA

Inventor： Hajime SAKAMOTO ,  Tadashi SUGIYAMA ,  Dongdong WANG ,  Takashi KARIYA

IPC: H05K3/42

CPC classification number: H01L24/29 ,  H01L21/4846 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/19 ,  H01L24/24 ,  H01L24/32 ,  H01L24/83 ,  H01L25/03 ,  H01L25/18 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2223/5448 ,  H01L2223/54486 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01043 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01052 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/18162 ,  H01L2924/30107 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/09036 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09918 ,  H05K2201/10674 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/3512 ,  H01L2924/00

Abstract: A method of manufacturing a multilayer printed circuit board having interlayer insulating layers and conductor layers repeatedly formed on a substrate, via holes formed in the interlayer insulating layers, and establishing electrical connection through the via holes, including containing an electronic component in said substrate, removing a film on a surface of a die pad of said electronic component, forming a mediate layer to be connected to a via hole of a lowermost interlayer insulating layer, on said die pad, forming the interlayer insulating layers on said substrate, and forming the via holes connected to the conductor circuits and the mediate layers, in said interlayer resin insulating layers.

Abstract translation: 一种制造多层印刷电路板的方法，所述多层印刷电路板具有层间绝缘层和重复形成在基板上的导体层，所述多层印刷电路板通过形成在所述层间绝缘层中的孔，并且通过所述通孔建立电连接，所述电连接包括在所述基板中包含电子部件， 在所述电子部件的芯片焊盘的表面上形成薄膜，在所述芯片焊盘上形成与最下层绝缘层的通路孔连接的中间层，在所述基板上形成层间绝缘层， 在所述层间树脂绝缘层中连接到导体电路和中间层的孔。

公开(公告)号：US20090064493A1

公开(公告)日：2009-03-12

申请号：US12255699

申请日：2008-10-22

Applicant: Takashi KARIYA ,  Hironori Tanaka

Inventor： Takashi KARIYA ,  Hironori Tanaka

IPC: H05K3/00

CPC classification number: H05K1/162 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/3011 ,  H05K3/4602 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0352 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09827 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  H01L2224/05599

Abstract: A printed circuit board including a conductor portion, an insulating layer formed over the conductor portion, a thin-film capacitor formed over the insulating layer and including a first electrode, a second electrode and a high-dielectric layer interposed between the first electrode and the second electrode, and a via-hole conductor structure formed through the second electrode and insulating layer and electrically connecting the second electrode and the conductor portion. The via-hole conductor structure has a first portion in the second electrode and a second portion in the insulating layer. The first portion of the via-hole conductor structure has a truncated-cone shape tapering toward the conductor portion.

Abstract translation: 一种印刷电路板，包括导体部分，在导体部分上形成的绝缘层，形成在绝缘层之上的薄膜电容器，并且包括第一电极，第二电极和介于第一电极和第二电极之间的高电介质层 第二电极和通过第二电极和绝缘层形成的通孔导体结构，并且电连接第二电极和导体部分。 通孔导体结构在第二电极中具有第一部分，在绝缘层中具有第二部分。 通孔导体结构的第一部分具有朝向导体部分逐渐变细的截锥形。

公开(公告)号：US20120302010A1

公开(公告)日：2012-11-29

申请号：US13561247

申请日：2012-07-30

Applicant: Takashi KARIYA ,  Akira Mochida

Inventor： Takashi KARIYA ,  Akira Mochida

IPC: H01L21/58

CPC classification number: H05K1/162 ,  H05K1/0231 ,  H05K1/0271 ,  H05K1/113 ,  H05K3/4602 ,  H05K2201/0133 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2201/10522 ,  H05K2201/10734

Abstract: A method for manufacturing a printed wiring board includes forming an uncalcined layer containing a raw ceramic material on a first metal layer, firing the uncalcined layer formed on the first metal layer such that a high dielectric constant layer having a ceramic body calcined in a sheet form is formed on the first metal layer, forming a second metal layer on the high dielectric constant layer on the opposite side of the high dielectric constant layer with respect to the first metal layer such that a layered capacitor having the high dielectric constant layer and first and second layer electrodes sandwiching the high dielectric constant layer is formed, and disposing the layered capacitor in a main body.

Abstract translation: 一种制造印刷电路板的方法包括在第一金属层上形成含有原料陶瓷材料的未煅烧层，焙烧形成在第一金属层上的未煅烧层，使得具有以片状形式煅烧的陶瓷体的高介电常数层 形成在第一金属层上，相对于第一金属层在高介电常数层的相对侧的高介电常数层上形成第二金属层，使得具有高介电常数层的层状电容器和第一金属层 形成夹着高介电常数层的第二层电极，并将层叠电容器配置在主体中。

公开(公告)号：US20110063806A1

公开(公告)日：2011-03-17

申请号：US12952759

申请日：2010-11-23

Applicant: Takashi KARIYA ,  Toshiki Furutani ,  Takeshi Kawanishi

Inventor： Takashi KARIYA ,  Toshiki Furutani ,  Takeshi Kawanishi

IPC: H05K1/18

CPC classification number: H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/112 ,  H05K3/4602 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2201/10674 ,  H01L2224/05599

Abstract: A circuit wiring board including a wiring substrate, multiple electronic components provided on a surface of the wiring substrate, and a heat resistant substrate accommodated in the wiring substrate and having a core substrate and a built-up wiring layer formed over the core substrate. The built-up wiring layer includes a conductive layer and an interlayer resin insulating layer, and the electronic components are electrically connected to the conductive layer of the built-up wiring layer.

Abstract translation: 一种电路布线板，包括布线基板，设置在所述布线基板的表面上的多个电子部件和容纳在所述布线基板中的耐热基板，并且具有形成在所述芯基板上的芯基板和积层布线层。 叠层布线层包括导电层和层间树脂绝缘层，并且电子部件电连接到组合布线层的导电层。

公开(公告)号：US20090255716A1

公开(公告)日：2009-10-15

申请号：US12488207

申请日：2009-06-19

Applicant: Takashi KARIYA ,  Toshiki FURUTANI ,  Takeshi KAWANISHI

Inventor： Takashi KARIYA ,  Toshiki FURUTANI ,  Takeshi KAWANISHI

IPC: H05K1/00

CPC classification number: H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/112 ,  H05K3/4602 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2201/10674 ,  H01L2224/05599

Abstract: A circuit wiring board including a wiring substrate, and a heat resistant substrate accommodated in the wiring substrate and having a thermal expansion coefficient in a range between 3 ppm to 10 ppm and including a core substrate and a built-up wiring layer formed over the core substrate, the built-up wiring layer including conductive layers, interlayer resin insulating layers and a via hole conductor connecting the conductive layers through one of the interlayer resin insulating layers.

Abstract translation: 一种电路布线板，包括布线基板和容纳在所述布线基板中的耐热基板，其热膨胀系数在3ppm至10ppm之间的范围内，并且包括芯基板和形成在所述芯上的积层布线层 衬底，包括导电层的积层布线层，层间树脂绝缘层和通过层间树脂绝缘层之一连接导电层的通孔导体。

公开(公告)号：US20090175011A1

公开(公告)日：2009-07-09

申请号：US12401127

申请日：2009-03-10

Applicant: Takashi KARIYA

Inventor： Takashi KARIYA

IPC: H05K1/18 ,  H05K7/00

CPC classification number: H01G4/30 ,  H01G4/232 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/66 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/81192 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/113 ,  H05K1/162 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/09518 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2203/0152 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: When a package substrate with a built-in capacitor includes a first thin-film small electrode 41aa and a second thin-film small electrode 42aa that are electrically short-circuited to each other via a pinhole P in a high-dielectric layer 43, a power supply post 61a and a via hole 61b are not formed in the first thin-film small electrode 41aa, and a ground post 62a and a via hole 62b are not formed in the second thin-film small electrode 42aa, either. As a result, the short-circuited small electrodes 41aa and 42aa are electrically connected to neither a power supply line nor a ground line, and become a potential independent from a power supply potential and a ground potential. Therefore, in the thin-film capacitor 40, only the portion where the short-circuited small electrodes 41aa and 42aa sandwich the high dielectric layer 43 loses the capacitor function, and portions where other thin-film small electrodes 41a and 42a sandwich the high dielectric layer 43 maintain the capacitor function.

Abstract translation: 当具有内置电容器的封装衬底包括通过高电介质层43中的针孔P彼此电短路的第一薄膜小电极41aa和第二薄膜小电极42aa时， 在第一薄膜小电极41aa中没有形成供电支柱61a和通孔61b，也不在第二薄膜小电极42aa中形成接地柱62a和通孔62b。 结果，短路的小电极41aa和42aa既不与电源线也不与接地线电连接，并且成为独立于电源电位和接地电位的电位。 因此，在薄膜电容器40中，只有短路的小电极41aa和42aa夹着高电介质层43的部分失去电容器功能，其他薄膜小电极41a和42a夹住高电介质的部分 层43保持电容器的功能。

公开(公告)号：US20090053911A1

公开(公告)日：2009-02-26

申请号：US12254608

申请日：2008-10-20

Applicant: Takashi KARIYA ,  Toshiki Furutani ,  Takeshi Kawanishi

Inventor： Takashi KARIYA ,  Toshiki Furutani ,  Takeshi Kawanishi

IPC: H01R12/02

CPC classification number: H05K3/4015 ,  H01L21/4853 ,  H01L23/49811 ,  H01L24/45 ,  H01L24/72 ,  H01L24/78 ,  H01L24/81 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1134 ,  H01L2224/131 ,  H01L2224/451 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/78301 ,  H01L2224/786 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/838 ,  H01L2224/851 ,  H01L2224/85205 ,  H01L2224/90 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3011 ,  H05K3/326 ,  H05K3/341 ,  H05K2201/10265 ,  H05K2201/10287 ,  H05K2203/049 ,  Y10T29/49135 ,  Y10T29/49142 ,  Y10T29/49149 ,  Y10T29/49153 ,  H01L2224/13099 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2224/48 ,  H01L2924/00015 ,  H01L2224/05599

Abstract: A printed circuit board according to the present invention is a printed circuit board (4) including a component mounting pin (1) made of a metal wire to connect with a semiconductor chip (10). The semiconductor chip (10) is a surface mounting type semiconductor chip having an electrode pad on its mounting surface for use in a flip-chip mounting system. The component mounting pin (1) is formed by using wire-bonding technology. This printed circuit board (4) is able to decrease malconnections or disconnection caused by a difference between the coefficients of thermal expansion of the semiconductor chip (10) and the printed circuit board (4).

公开(公告)号：US20090000812A1

公开(公告)日：2009-01-01

申请号：US12163286

申请日：2008-06-27

Applicant: Takashi KARIYA

Inventor： Takashi KARIYA

IPC: H05K1/16 ,  H05K3/30

CPC classification number: H01L23/49838 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/16227 ,  H05K1/113 ,  H05K1/115 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0352 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/10674 ,  Y10T29/49139

Abstract: A multilayer printed wiring board includes a core substrate and a built-up wiring layer formed by alternately layering conductor circuits and insulating resin layers. The built-up wiring layer includes a first surface provided in contact with the core substrate and a second surface opposing the first surface and including a mounting area on which at least one semiconductor device is to be mounted. A first plurality of through-hole conductors is formed in a first portion of the core substrate which corresponds to the mounting area of the second surface, and a second plurality of through-hole conductors formed in a second portion of the core substrate which corresponds to another area of the second surface other than the mounting area. A pitch between the first plurality of through-hole conductors is smaller than a pitch between the second plurality of through-hole conductors. In one aspect, a ratio of pads to through holes directly below a processor core section of the semiconductor device is less that a number of pads to through holes in an area outside the processor core.

Abstract translation: 多层印刷电路板包括芯基板和通过交替层叠导体电路和绝缘树脂层而形成的积层布线层。 所述积层布线层包括与所述芯基板接触的第一表面和与所述第一表面相对的第二表面，并且包括将要安装至少一个半导体器件的安装区域。 第一多个通孔导体形成在芯基板的与第二表面的安装区域对应的第一部分中，第二多个通孔导体形成在芯基板的第二部分中，其对应于 第二表面的另一区域，而不是安装区域。 第一多个通孔导体之间的间距小于第二多个通孔导体之间的节距。 在一个方面，焊盘与半导体器件的处理器核心部分正下方的通孔的比例小于处理器核心外部区域中通孔的数量。