公开(公告)号：US20100200285A1

公开(公告)日：2010-08-12

申请号：US12763455

申请日：2010-04-20

Applicant: Takashi KARIYA ,  Hironori Tanaka

Inventor： Takashi KARIYA ,  Hironori Tanaka

IPC: H05K1/16 ,  C23C14/34 ,  H01G4/06 ,  H01G4/008

CPC classification number: H05K1/162 ,  H01L21/4867 ,  H01L23/498 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K3/388 ,  H05K3/4602 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0195 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09718 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A method of producing a capacitor for a printed circuit board includes producing high-dielectric sheets and selecting ones of the high-dielectric sheets, which are substantially free from a defect after the heat process. Each of the high-dielectric sheets is produced by providing a first electrode, forming a first sputter film on the first electrode, forming an intermediate layer on the first sputter film by calcining a sol-gel film, forming a second sputter film on the intermediate layer, and providing a second electrode on the second sputter film. The high-dielectric sheets are subjected to a heat process in which the high-dielectric sheets are subjected to a first temperature at least once and a second temperature higher than the first temperature at least once.

Abstract translation: 一种印刷电路板用电容器的制造方法，其特征在于，制造高介电质片材，并选择在热处理后基本上不存在缺陷的高电介质片材。 每个高电介质片通过提供第一电极来制造，在第一电极上形成第一溅射膜，通过煅烧溶胶 - 凝胶膜在第一溅射膜上形成中间层，在中间层上形成第二溅射膜 并且在第二溅射膜上提供第二电极。 对高电介质片材进行热处理，其中高电介质片材经受至少一次的第一温度和比第一温度高至少一次的第二温度。

公开(公告)号：US20090200639A1

公开(公告)日：2009-08-13

申请号：US12401166

申请日：2009-03-10

Applicant: Takashi KARIYA

Inventor： Takashi KARIYA

IPC: H01L29/92 ,  H01L23/52

CPC classification number: H01G4/30 ,  H01G4/232 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/66 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/81192 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/113 ,  H05K1/162 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/09518 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2203/0152 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: When a package substrate with a built-in capacitor includes a first thin-film small electrode 41aa and a second thin-film small electrode 42aa that are electrically short-circuited to each other via a pinhole P in a high-dielectric layer 43, a power supply post 61a and a via hole 61b are not formed in the first thin-film small electrode 41aa, and a ground post 62a and a via hole 62b are not formed in the second thin-film small electrode 42aa, either. As a result, the short-circuited small electrodes 41aa and 42aa are electrically connected to neither a power supply line nor a ground line, and become a potential independent from a power supply potential and a ground potential. Therefore, in the thin-film capacitor 40, only the portion where the short-circuited small electrodes 41aa and 42aa sandwich the high dielectric layer 43 loses the capacitor function, and portions where other thin-film small electrodes 41a and 42a sandwich the high dielectric layer 43 maintain the capacitor function.

公开(公告)号：US20090200069A1

公开(公告)日：2009-08-13

申请号：US12419007

申请日：2009-04-06

Applicant: Takashi KARIYA ,  Akira Mochida

Inventor： Takashi KARIYA ,  Akira Mochida

IPC: H05K1/03 ,  H05K1/11 ,  H05K1/16 ,  H05K1/09

CPC classification number: H05K1/162 ,  H05K1/0231 ,  H05K1/0271 ,  H05K1/113 ,  H05K3/4602 ,  H05K2201/0133 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2201/10522 ,  H05K2201/10734

Abstract: A multilayer printed wiring board 10 includes: a mounting portion 60 on the top surface of which is mounted a semiconductor element that is electrically connected to a wiring pattern 32, etc.; and a capacitor portion 40 having a high dielectric constant layer 43, formed of ceramic and first and second layer electrodes 41 and 42 that sandwich the high dielectric constant layer 43. One of either of the first and second layer electrodes 41 and 42 is connected to a power supply line of the semiconductor element and the other of either of the first and second layer electrodes 41 and 42 is connected to a ground line. In this multilayer printed wiring board 10, high dielectric constant layer 43 included in the layered capacitor portion 40, which is connected between the power supply line and the ground line, is formed of ceramic. With this structure, the static capacitance of the layered capacitor portion 40 can be high, and an adequate decoupling effect is exhibited even under circumstances in which instantaneous potential drops occur readily.

Abstract translation: 多层印刷电路板10包括：安装部分60，其顶表面上安装有电连接到布线图案32的半导体元件; 以及具有由陶瓷形成的高介电常数层43的电容器部分40和夹在高介电常数层43上的第一和第二层电极41和42。第一和第二层电极41和42中的一个连接到 半导体元件的电源线和第一和第二层电极41和42中的另一个连接到接地线。 在这种多层印刷电路板10中，连接在电源线和接地线之间的层状电容器部分40中包括的高介电常数层43由陶瓷形成。 利用这种结构，层状电容器部分40的静态电容可以很高，并且即使在容易发生瞬时电位下降的情况下也可以发挥足够的去耦效应。

公开(公告)号：US20080104833A1

公开(公告)日：2008-05-08

申请号：US11964355

申请日：2007-12-26

Applicant: Takashi KARIYA ,  Akira MOCHIDA

Inventor： Takashi KARIYA ,  Akira MOCHIDA

IPC: H05K3/30 ,  H01K3/10 ,  H05K3/10 ,  H05K1/00

CPC classification number: H01L21/6835 ,  H01L21/4857 ,  H01L2221/68345 ,  H01L2221/68363 ,  H01L2224/05001 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/0102 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H05K1/162 ,  H05K3/4602 ,  H05K2201/0175 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09718 ,  H05K2203/0353 ,  Y10T29/435 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: In a printed wiring board 10, an upper electrode connecting portion 52 penetrates through a capacitor portion 40 in top to bottom direction so that an upper electrode connecting portion first part 52a is not in contact with the capacitor portion 40, passes through an upper electrode connecting portion third part 52c provided at the upper portion of the capacitor portion 40, and then connects from the upper electrode connecting portion second part 52b to an upper electrode 42. Furthermore, a lower electrode connecting portion 51 penetrates through the capacitor portion 40 in top to bottom direction so that it is not in contact with the upper electrode 42 of the capacitor portion 40, but is in contact with a lower electrode 41. Therefore, the upper electrode connecting portion 52 and the lower electrode connecting portion 51 can be formed even after in process of build-up, the whole surface is covered by a high dielectric capacitor sheet that has a structure that a high dielectric layer is sandwiched between two metal foils and will afterwards serve as the capacitor portion 40.

Abstract translation: 在印刷布线板10中，上部电极连接部52从上下方向贯穿电容器部40，使上部电极连接部第一部分52a不与电容器部40接触，通过上部电极 连接部分第三部分52c设置在电容器部分40的上部，然后从上电极连接部分第二部分52b连接到上电极42。 此外，下电极连接部51从上下方向贯通电容器部40，使其不与电容器部40的上部电极42接触，而与下部电极41接触。 因此，上部电极连接部52和下部电极连接部51即使在积聚的过程中也可以形成，整个表面被高介电电容器片覆盖，该介电电容片具有将介电层夹在高介电层之间的结构 两个金属箔，然后用作电容器部分40。

公开(公告)号：US20110259629A1

公开(公告)日：2011-10-27

申请号：US13175683

申请日：2011-07-01

Applicant: Takashi KARIYA ,  Hironori Tanaka

Inventor： Takashi KARIYA ,  Hironori Tanaka

IPC: H05K1/09 ,  H05K1/18 ,  H05K1/02

CPC classification number: H05K1/162 ,  H01L21/4867 ,  H01L23/498 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K3/388 ,  H05K3/4602 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0195 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09718 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A method of producing a capacitor for a printed circuit board includes producing high-dielectric sheets and selecting ones of the high-dielectric sheets, which are substantially free from a defect after the heat process. Each of the high-dielectric sheets is produced by providing a first electrode, forming a first sputter film on the first electrode, forming an intermediate layer on the first sputter film by calcining a sol-gel film, forming a second sputter film on the intermediate layer, and providing a second electrode on the second sputter film. The high-dielectric sheets are subjected to a heat process in which the high-dielectric sheets are subjected to a first temperature at least once and a second temperature higher than the first temperature at least once.

Abstract translation: 一种印刷电路板用电容器的制造方法，其特征在于，制造高介电质片材，并选择在热处理后基本上不存在缺陷的高电介质片材。 每个高电介质片通过提供第一电极来制造，在第一电极上形成第一溅射膜，通过煅烧溶胶 - 凝胶膜在第一溅射膜上形成中间层，在中间层上形成第二溅射膜 并且在第二溅射膜上提供第二电极。 对高电介质片材进行热处理，其中高电介质片材经受至少一次的第一温度和比第一温度高至少一次的第二温度。

公开(公告)号：US20100200279A1

公开(公告)日：2010-08-12

申请号：US12647015

申请日：2009-12-24

Applicant: Takashi KARIYA ,  Daiki Komatsu

Inventor： Takashi KARIYA ,  Daiki Komatsu

IPC: H05K1/03 ,  H05K3/10

CPC classification number: H05K1/162 ,  H01L21/486 ,  H01L23/145 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/112 ,  H05K3/108 ,  H05K3/4682 ,  H05K3/4688 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/09436 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/096 ,  Y10T29/4916 ,  H01L2924/00 ,  H01L2224/0401

Abstract: An electronic component mounting substrate including a support layer made of resin with first and second surfaces, an organic insulation layer on the first surface of the support layer with a first surface on opposite side of the first surface of the support layer and a second surface in contact with the first surface of the support layer, an inorganic insulation layer on the first surface of the organic layer, a conductor on the second surface of the support layer, and a first conductive circuit on the second surface of the organic layer. The inorganic layer has a second conductive circuit and a pad for mounting an electronic component inside the inorganic layer. The organic layer has a via conductor inside the organic layer and connecting the first and second circuits. The support layer has a conductive post inside the support layer and connecting the first circuit and the conductor.

Abstract translation: 一种电子部件安装基板，包括由具有第一表面和第二表面的树脂制成的支撑层，在所述支撑层的第一表面上的有机绝缘层，在所述支撑层的第一表面的相对侧上具有第一表面， 与支撑层的第一表面接触，有机层的第一表面上的无机绝缘层，支撑层的第二表面上的导体和在有机层的第二表面上的第一导电电路。 无机层具有第二导电电路和用于将电子部件安装在无机层内部的焊盘。 有机层在有机层内部具有通孔导体并连接第一和第二电路。 支撑层在支撑层内部具有导电柱并连接第一电路和导体。

公开(公告)号：US20090090547A1

公开(公告)日：2009-04-09

申请号：US12331054

申请日：2008-12-09

Applicant: Takashi KARIYA ,  Toshiki Furutani

Inventor： Takashi KARIYA ,  Toshiki Furutani

IPC: H05K1/16 ,  H05K1/11

CPC classification number: H05K1/0271 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K1/0373 ,  H05K1/115 ,  H05K3/28 ,  H05K3/4007 ,  H05K3/4602 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/068 ,  H05K2201/10674 ,  Y10T29/49126 ,  Y10T29/49151 ,  Y10T29/49162 ,  H01L2224/0401

Abstract: A multilayer printed wiring board 10 includes: a build-up layer that is formed on a core substrate 20 and has a conductor pattern disposed on an upper surface; a low elastic modulus layer 40 that is formed on the build-up layer 30; lands 52 that are disposed on an upper surface of the low elastic modulus layer 40 and connected via solder bumps 66 to a IC chip 70; and conductor posts 50 that pass through the low elastic modulus layer 40 and electrically connect lands 52 with conductor patterns 32. The conductor posts 50 have the aspect ratio Rasp (height/minimum diameter) of not less than 4 and the minimum diameter exceeding 30 μm, and the aspect ratio Rasp of external conductor posts 50a, which are positioned at external portions of the low elastic modulus layer 40, is greater than or equal to the aspect ratio Rasp of internal conductor posts 50b, which are positioned at internal portions of the low elastic modulus layer 40.

Abstract translation: 多层印刷布线板10包括：形成在芯基板20上并具有布置在上表面上的导体图案的堆积层; 形成在积层30上的低弹性模量层40; 焊盘52设置在低弹性模量层40的上表面上并通过焊料凸块66连接到IC芯片70; 以及穿过低弹性模量层40并将焊盘52与导体图案32电连接的导体柱50.导体柱50的纵横比Rasp（高度/最小直径）不小于4，最小直径超过30μm ，并且位于低弹性模量层40的外部的外部导体柱50a的纵横比Rasp大于或等于位于内部导体柱50b的内部导体柱50b的纵横比Rasp 低弹性模量层40。

公开(公告)号：US20090084594A1

公开(公告)日：2009-04-02

申请号：US12330147

申请日：2008-12-08

Applicant: Takashi KARIYA ,  Toshiki FURUTANI ,  Takeshi KAWANISHI

Inventor： Takashi KARIYA ,  Toshiki FURUTANI ,  Takeshi KAWANISHI

IPC: H05K1/11 ,  H05K1/16

CPC classification number: H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/112 ,  H05K3/4602 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2201/10674 ,  H01L2224/05599

Abstract: This invention provides a multilayer printed wiring board which achieves fine pitches. A heat resistant substrate is incorporated in a multilayer printed wiring board and interlayer resin insulation layer and conductive layer are placed alternately on the heat resistant substrate. A built-up wiring board in which respective conductive layers are connected by via hole is formed. A via hole is formed on the surface of a mirror-processed Si substrate by using a heat resistant substrate composed of Si substrate so that finer wiring than a resin substrate having unevenness in its surface can be formed, whereby achieving fine pitches. Further, by forming the wiring on a mirror processed surface, dispersion of wiring decreases thereby decreasing dispersion of impedance.

Abstract translation: 本发明提供一种实现细小间距的多层印刷线路板。 在多层印刷线路板和层间树脂绝缘层中并入耐热基板，并将导电层交替放置在耐热基板上。 形成各导电层通过通孔连接的叠层布线板。 通过使用由Si衬底构成的耐热衬底，在镜面处理的Si衬底的表面上形成通孔，从而可以形成比其表面不均匀的树脂衬底更细的布线，从而实现细小的间距。 此外，通过在镜面处理表面上形成布线，布线的分散减小，从而减小阻抗的分散。

公开(公告)号：US20120032335A1

公开(公告)日：2012-02-09

申请号：US13205027

申请日：2011-08-08

Applicant: Takashi KARIYA ,  Toshiki Furutani ,  Shinobu Kato

Inventor： Takashi KARIYA ,  Toshiki Furutani ,  Shinobu Kato

IPC: H01L23/48 ,  H01L21/60

CPC classification number: H01L24/19 ,  H01L21/568 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L24/06 ,  H01L24/17 ,  H01L24/20 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/06135 ,  H01L2224/06177 ,  H01L2224/12105 ,  H01L2224/13 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73217 ,  H01L2224/81192 ,  H01L2224/9202 ,  H01L2224/92124 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/351 ,  H01L2924/00

Abstract: An electronic component including a wiring board having a power-source pattern and a signal pattern, a semiconductor element mounted on the wiring board and having a power-source electrode pad and a signal electrode pad, a first connection portion being made of a conductive material and connecting the signal pattern of the wiring board and the signal electrode pad of the semiconductor element, and a second connection portion being made of a conductive material and connecting the power-source pattern of the wiring board and the power-source electrode pad of the semiconductor element. The conductive material of the first connection portion and the conductive material of the second connection portion are selected such that the conductive material of the second connection portion has an electrical resistance which is lower than an electrical resistance of the conductive material of the first connection portion.

Abstract translation: 一种电子部件，包括具有电源图案和信号图案的布线板，安装在布线基板上并具有电源电极焊盘和信号电极焊盘的半导体元件，第一连接部分由导电材料制成 并且连接所述布线板的信号图案和所述半导体元件的信号电极焊盘;以及第二连接部，其由导电材料制成，并且将所述布线板的电源图案和所述电源电极焊盘 半导体元件。 选择第一连接部分的导电材料和第二连接部分的导电材料，使得第二连接部分的导电材料具有低于第一连接部分的导电材料的电阻的电阻。

公开(公告)号：US20110063811A1

公开(公告)日：2011-03-17

申请号：US12948894

申请日：2010-11-18

Applicant: Takashi KARIYA ,  Akira Mochida

Inventor： Takashi KARIYA ,  Akira Mochida

IPC: H05K1/16

CPC classification number: H05K1/162 ,  H05K1/0231 ,  H05K1/0271 ,  H05K1/113 ,  H05K3/4602 ,  H05K2201/0133 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2201/10522 ,  H05K2201/10734

Abstract: A printed wiring board includes a main body having a mounting portion and ground and power supply pads in the mounting portion such that a ground line of a semiconductor device is connected to a ground pad and a power supply line of the device is connected to a power supply pad, and a layered capacitor disposed in the main body and having a high dielectric constant layer and first and second layer electrodes sandwiching the dielectric layer. One of the electrodes is connected to the power supply line and the other electrode is connected to the ground line, the first electrode has a solid pattern including passage holes through which second rod terminals connected to the second electrode pass in a non-contacting manner, and the second electrode has a solid pattern including passage holes through which first rod terminals connected to the first electrode pass in a non-contacting manner.

Abstract translation: 一种印刷电路板，包括具有安装部分的主体和安装部分中的接地和电源焊盘，使得半导体器件的接地线连接到接地焊盘，并且该设备的电源线连接到电源 供电焊盘和设置在主体中并具有高介电常数层的层状电容器和夹着介电层的第一和第二层电极。 电极中的一个连接到电源线，另一个电极连接到接地线，第一电极具有固体图案，其包括通孔，第二电极与第二电极连接，第二电极以非接触的方式通过， 并且第二电极具有固体图案，其包括通孔，通过该通孔与第一电极连接的第一杆端子以非接触方式通过。