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    METAL GATE TRANSISTOR AND METHOD FOR FABRICATING THE SAME
    12.
    发明申请
    METAL GATE TRANSISTOR AND METHOD FOR FABRICATING THE SAME 有权
    金属栅极晶体管及其制造方法

    公开(公告)号：US20150076623A1

    公开(公告)日：2015-03-19

    申请号：US14025833

    申请日：2013-09-13

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Shih-Fang Tzou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Hung-Yi Wu ,  Tong-Jyun Huang ,  Chien-Ting Lin ,  Chun-Hsien Lin

    IPC: H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8238

    CPC classification number: H01L29/4966 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/42364 ,  H01L29/66545

    Abstract: A method for fabricating metal gate transistor is disclosed. The method includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a dummy gate on each of the NMOS region and the PMOS region respectively; removing the dummy gates from each of the NMOS region and the PMOS region; forming a n-type work function layer on the NMOS region and the PMOS region; removing the n-type work function layer in the PMOS region; forming a p-type work function layer on the NMOS region and the PMOS region; and depositing a low resistance metal layer on the p-type work function layer of the NMOS region and the PMOS region.

    Abstract translation: 公开了一种用于制造金属栅极晶体管的方法。 该方法包括以下步骤：提供具有NMOS区和PMOS区的衬底; 在NMOS区域和PMOS区域分别形成虚拟栅极; 从所述NMOS区域和所述PMOS区域中的每一个去除所述伪栅极; 在NMOS区域和PMOS区域上形成n型功函数层; 去除PMOS区域中的n型功函数层; 在NMOS区域和PMOS区域上形成p型功函数层; 以及在NMOS区域和PMOS区域的p型功函数层上沉积低电阻金属层。

    FINFET LDMOS DEVICE
    13.
    发明申请
    FINFET LDMOS DEVICE 有权

    公开(公告)号：US20250151320A1

    公开(公告)日：2025-05-08

    申请号：US18531668

    申请日：2023-12-06

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Yi Chuen Eng ,  Tzu-Feng Chang ,  Teng-Chuan Hu ,  Yi-Wen Chen ,  Yu-Hsiang Lin

    IPC: H01L29/78

    Abstract: A FinFET LDMOS device includes a semiconductor substrate; juxtaposed first well and second well in the semiconductor substrate; semiconductor fins extending on the semiconductor substrate along a first direction, the semiconductor fins including a first fin portion in the first well and a second fin portion in the second well; an extra semiconductor body adjoining the first fin portion and the second fin portion and extending along a second direction; a source region on the first fin portion; a drain region on the second fin portion; a gate covering the semiconductor fin and extending along the second direction, wherein the gate partially overlaps the first fin portion and partially overlaps the second fin portion, and the extra semiconductor body is covered by the gate; and a single-diffusion break structure embedded in the second fin portion and between the gate and drain region.

    METHOD FOR PHYSICALLY UNCLONABLE FUNCTION THROUGH GATE HEIGHT TUNING
    14.
    发明申请
    METHOD FOR PHYSICALLY UNCLONABLE FUNCTION THROUGH GATE HEIGHT TUNING 有权

    公开(公告)号：US20250017003A1

    公开(公告)日：2025-01-09

    申请号：US18230174

    申请日：2023-08-04

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chang-Yih Chen ,  Yi-Wen Chen ,  Wei-Chung Sun

    IPC: H10B20/00 ,  G06F21/75

    Abstract: A method for physically unclonable function through gate height tuning is provided in the present invention, including steps of forming a high-k dielectric layer and a dummy silicon layer on a semiconductor substrate, removing the dummy silicon layer, forming a work function layer and a metal filling layer on the high-k dielectric layer, and performing a CMP process to remove the metal filling layer, so as to form metal gates with heights lower than a critical gate height, and using the metal gates to manufacture PIO pairs in an internal bias generator. Since the height of metal gates is lower than the critical gate height, a local threshold voltage mismatching of the programmed I/O (PIO) pairs becomes larger, so as to achieve random code generation in physically unclonable function (PUF).

    METHOD OF FORMING SEMICONDUCTOR DEVICE
    16.
    发明申请
    METHOD OF FORMING SEMICONDUCTOR DEVICE 有权
    形成半导体器件的方法

    公开(公告)号：US20160099179A1

    公开(公告)日：2016-04-07

    申请号：US14506009

    申请日：2014-10-03

    Applicant: United Microelectronics Corp.

    Inventor： Chun-Tsen Lu ,  Chih-Jung Su ,  Jian-Wei Chen ,  Shui-Yen Lu ,  Yi-Wen Chen ,  Po-Cheng Huang ,  Chen-Ming Huang ,  Shih-Fang Tzou

    IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/311 ,  H01L21/02 ,  H01L29/06 ,  H01L21/3105

    CPC classification number: H01L29/66545 ,  H01L21/0206 ,  H01L21/02065 ,  H01L21/02271 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/311 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/4966 ,  H01L29/517

    Abstract: A method of forming a semiconductor device is disclosed. A substrate having multiple fins is provided. An insulating layer fills a lower portion of a gap between two adjacent fins. At least one first stacked structure is formed on one fin and at least one second stacked structure is formed on one insulation layer. A first dielectric layer is formed to cover the first and second stacked structures. A portion of the first dielectric layer and portions of the first and second stacked structures are removed. Another portion of the first dielectric layer is removed until a top of the remaining first dielectric layer is lower than tops of the first and second stacked structures. A second dielectric layer is formed to cover the first and second stacked structures. A portion of the second dielectric layer is removed until the tops of the first and second stacked structures are exposed.

    Abstract translation: 公开了一种形成半导体器件的方法。 提供具有多个翅片的基板。 绝缘层填充两个相邻翅片之间的间隙的下部。 在一个翅片上形成至少一个第一堆叠结构，并且在一个绝缘层上形成至少一个第二堆叠结构。 形成第一电介质层以覆盖第一和第二堆叠结构。 去除第一电介质层的一部分和第一和第二堆叠结构的部分。 去除第一电介质层的另一部分，直到剩余的第一电介质层的顶部低于第一和第二堆叠结构的顶部。 形成第二电介质层以覆盖第一和第二堆叠结构。 去除第二电介质层的一部分直到第一和第二堆叠结构的顶部露出。

    METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
    17.
    发明申请
    METHOD FOR FABRICATING SEMICONDUCTOR DEVICE 审中-公开
    制造半导体器件的方法

    公开(公告)号：US20160035854A1

    公开(公告)日：2016-02-04

    申请号：US14881162

    申请日：2015-10-13

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Shih-Fang Tzou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Hung-Yi Wu ,  Tong-Jyun Huang ,  Chien-Ting Lin ,  Chun-Hsien Lin

    IPC: H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8238

    CPC classification number: H01L29/4966 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/42364 ,  H01L29/66545

    Abstract: A method for fabricating metal gate transistor is disclosed. The method includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a dummy gate on each of the NMOS region and the PMOS region respectively; removing the dummy gates from each of the NMOS region and the PMOS region; forming a n-type work function layer on the NMOS region and the PMOS region; removing the n-type work function layer in the PMOS region; forming a p-type work function layer on the NMOS region and the PMOS region; and depositing a low resistance metal layer on the p-type work function layer of the NMOS region and the PMOS region.

    Abstract translation: 公开了一种用于制造金属栅极晶体管的方法。 该方法包括以下步骤：提供具有NMOS区和PMOS区的衬底; 在NMOS区域和PMOS区域分别形成虚拟栅极; 从所述NMOS区域和所述PMOS区域中的每一个去除所述伪栅极; 在NMOS区域和PMOS区域上形成n型功函数层; 去除PMOS区域中的n型功函数层; 在NMOS区域和PMOS区域上形成p型功函数层; 以及在NMOS区域和PMOS区域的p型功函数层上沉积低电阻金属层。

    SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME
    18.
    发明申请
    SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME 有权
    其半导体结构及其制造方法

    公开(公告)号：US20150243754A1

    公开(公告)日：2015-08-27

    申请号：US14187701

    申请日：2014-02-24

    Applicant: United Microelectronics Corp.

    Inventor： Hung-Yi Wu ,  Chien-Ming Lai ,  Yi-Wen Chen

    IPC: H01L29/49 ,  H01L29/40

    CPC classification number: H01L29/4966 ,  H01L29/401 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/78

    Abstract: A semiconductor structure and a manufacturing method thereof are disclosed. The semiconductor structure includes an isolation layer, a gate dielectric layer, a first work function metal, a first bottom barrier layer, a second work function metal, and a first top barrier layer. The isolation layer is formed on a substrate and has a first gate trench. The gate dielectric layer is formed in the first gate trench. The first work function metal is formed on the gate dielectric layer in the first gate trench. The first bottom barrier layer is formed on the first work function metal. The second work function metal is formed on the first bottom barrier layer. The first top barrier layer is formed on the second work function metal.

    Abstract translation: 公开了一种半导体结构及其制造方法。 半导体结构包括隔离层，栅介质层，第一功函数金属，第一底阻挡层，第二功函数金属和第一顶阻挡层。 隔离层形成在衬底上并具有第一栅极沟槽。 栅介质层形成在第一栅极沟槽中。 第一功函数金属形成在第一栅极沟槽中的栅介质层上。 第一底部阻挡层形成在第一功函数金属上。 第二功能金属形成在第一底部阻挡层上。 第一顶部阻挡层形成在第二功函数金属上。

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