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    ACCESS SIGNAL ADJUSTMENT CIRCUITS AND METHODS FOR MEMORY CELLS IN A CROSS-POINT ARRAY
    11.
    发明申请
    ACCESS SIGNAL ADJUSTMENT CIRCUITS AND METHODS FOR MEMORY CELLS IN A CROSS-POINT ARRAY 有权
    交叉点信息调整电路和存储单元的方法

    公开(公告)号：US20150179250A1

    公开(公告)日：2015-06-25

    申请号：US14624891

    申请日：2015-02-18

    Applicant: Unity Semiconductor Corporation

    Inventor： Christophe J. Chevallier ,  Chang Hua Siau

    IPC: G11C13/00

    CPC classification number: G11C13/0033 ,  G11C11/21 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069

    Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to generate access signals to facilitate memory operations in scaled arrays of memory elements, such as memory implemented in third dimensional memory technology formed BEOL directly on top of a FEOL substrate that includes data access circuitry. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements disposed among word lines and subsets of bit lines, and an access signal generator. The access signal generator can be configured to modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. The modified magnitude can be a function of the position of the resistive memory element in the cross-point array.

    Abstract translation: 本发明的实施例一般涉及半导体和存储器技术，更具体地涉及系统，集成电路和方法，用于产生存取信号以促进存储器元件的按比例排列的存储器操作，诸如在形成的第三维存储器技术中实现的存储器 直接位于包含数据访问电路的FEOL基板之上。 在至少一些实施例中，非易失性存储器件可以包括具有布置在字线和位线子集之间的电阻性存储器元件的交叉点阵列和存取信号发生器。 访问信号发生器可被配置为修改信号的大小以产生用于信号访问与字线和位线子集相关联的电阻性存储器元件的修改幅度。 修改的幅度可以是交叉点阵列中的电阻性存储元件的位置的函数。

    Access signal adjustment circuits and methods for memory cells in a cross-point array
    12.
    发明授权
    Access signal adjustment circuits and methods for memory cells in a cross-point array 有权
    交叉点阵列中存储单元的访问信号调整电路和方法

    公开(公告)号：US08988930B2

    公开(公告)日：2015-03-24

    申请号：US14150521

    申请日：2014-01-08

    Applicant: Unity Semiconductor Corporation

    Inventor： Christophe J. Chevallier ,  Chang Hua Siau

    IPC: G11C11/00 ,  G11C13/00 ,  G11C11/21

    CPC classification number: G11C13/0033 ,  G11C11/21 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069

    Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to generate access signals to facilitate memory operations in scaled arrays of memory elements, such as memory implemented in third dimensional memory technology formed BEOL directly on top of a FEOL substrate that includes data access circuitry. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements disposed among word lines and subsets of bit lines, and an access signal generator. The access signal generator can be configured to modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. The modified magnitude can be a function of the position of the resistive memory element in the cross-point array.

    Abstract translation: 本发明的实施例一般涉及半导体和存储器技术，更具体地涉及系统，集成电路和方法，用于产生存取信号以促进存储器元件的按比例排列的存储器操作，诸如在形成的第三维存储器技术中实现的存储器 直接位于包含数据访问电路的FEOL基板之上。 在至少一些实施例中，非易失性存储器件可以包括具有布置在字线和位线子集之间的电阻性存储器元件的交叉点阵列和存取信号发生器。 访问信号发生器可被配置为修改信号的大小以产生用于信号访问与字线和位线子集相关联的电阻性存储器元件的修改幅度。 修改的幅度可以是交叉点阵列中的电阻性存储元件的位置的函数。

    Access signal adjustment circuits and methods for memory cells in a cross-point array
    18.
    发明授权
    Access signal adjustment circuits and methods for memory cells in a cross-point array 有权
    交叉点阵列中存储单元的访问信号调整电路和方法

    公开(公告)号：US09514811B2

    公开(公告)日：2016-12-06

    申请号：US15052627

    申请日：2016-02-24

    Applicant: UNITY SEMICONDUCTOR CORPORATION

    Inventor： Christophe J. Chevallier ,  Chang Hua Siau

    IPC: G11C11/00 ,  G11C13/00 ,  G11C11/21

    CPC classification number: G11C13/0033 ,  G11C11/21 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069

    Abstract: Systems, integrated circuits, and methods to generate access signals to facilitate memory operations in scaled arrays of memory elements, are described. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements and an access signal generator. The access signal generator can be configured to access a resistive memory element in the cross-point array.

    Abstract translation: 描述了用于产生访问信号的系统，集成电路和方法以促进存储器元件的缩放阵列中的存储器操作。 在至少一些实施例中，非易失性存储器件可以包括具有电阻存储器元件和存取信号发生器的交叉点阵列。 访问信号发生器可被配置为访问交叉点阵列中的电阻性存储器元件。

    ACCESS SIGNAL ADJUSTMENT CIRCUITS AND METHODS FOR MEMORY CELLS IN A CROSS-POINT ARRAY
    19.
    发明申请
    ACCESS SIGNAL ADJUSTMENT CIRCUITS AND METHODS FOR MEMORY CELLS IN A CROSS-POINT ARRAY 有权
    交叉点信息调整电路和存储单元的方法

    公开(公告)号：US20160172025A1

    公开(公告)日：2016-06-16

    申请号：US15052627

    申请日：2016-02-24

    Applicant: UNITY SEMICONDUCTOR CORPORATION

    Inventor： Christophe J. Chevallier ,  Chang Hua Siau

    IPC: G11C13/00

    CPC classification number: G11C13/0033 ,  G11C11/21 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069

    Abstract: Systems, integrated circuits, and methods to generate access signals to facilitate memory operations in scaled arrays of memory elements, are described. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements and an access signal generator. The access signal generator can be configured to access a resistive memory element in the cross-point array.

    Abstract translation: 描述了用于产生访问信号的系统，集成电路和方法以促进存储器元件的缩放阵列中的存储器操作。 在至少一些实施例中，非易失性存储器件可以包括具有电阻存储器元件和存取信号发生器的交叉点阵列。 访问信号发生器可被配置为访问交叉点阵列中的电阻性存储器元件。

    Access signal adjustment circuits and methods for memory cells in a cross-point array
    20.
    发明授权
    Access signal adjustment circuits and methods for memory cells in a cross-point array 有权

    公开(公告)号：US09299427B2

    公开(公告)日：2016-03-29

    申请号：US14624891

    申请日：2015-02-18

    Applicant: Unity Semiconductor Corporation

    Inventor： Christophe J. Chevallier ,  Chang Hua Siau

    IPC: G11C13/00 ,  G11C11/21

    CPC classification number: G11C13/0033 ,  G11C11/21 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069

    Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to generate access signals to facilitate memory operations in scaled arrays of memory elements, such as memory implemented in third dimensional memory technology formed BEOL directly on top of a FEOL substrate that includes data access circuitry. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements disposed among word lines and subsets of bit lines, and an access signal generator. The access signal generator can be configured to modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. The modified magnitude can be a function of the position of the resistive memory element in the cross-point array.

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