公开(公告)号：US08156252B2

公开(公告)日：2012-04-10

申请号：US12702998

申请日：2010-02-09

Applicant: Ryan McDaniel

Inventor： Ryan McDaniel

IPC: G06F3/00

CPC classification number: G06F13/4027

Abstract: In various embodiments, options for data striping to FLASH memory are provided. In one embodiment, an apparatus is provided. The apparatus includes an SATA to ATA bridge, an ATA to USB bridge coupled to the SATA to ATA bridge, and a USB interface coupled to the ATA to USB bridge. The apparatus also includes a first FLASH memory controller coupled to the USB interface. The apparatus further includes a first FLASH memory module coupled to the first FLASH memory controller. The apparatus also includes a second FLASH memory controller coupled to the USB interface and a second FLASH memory module coupled to the second FLASH memory controller. A method for block striping data to or from a plurality of read or write channels.

Abstract translation: 在各种实施例中，提供了用于数据条带化到闪速存储器的选项。 在一个实施例中，提供了一种装置。 该装置包括SATA到ATA桥，连接到SATA到ATA桥的ATA到USB桥，以及耦合到ATA到USB桥的USB接口。 该装置还包括耦合到USB接口的第一FLASH存储器控制器。 该装置还包括耦合到第一FLASH存储器控制器的第一FLASH存储器模块。 该装置还包括耦合到USB接口的第二闪速存储器控制器和耦合到第二闪速存储器控制器的第二闪速存储器模块。 一种用于将数据分离到多个读取或写入通道的数据的方法。

公开(公告)号：US20080155378A1

公开(公告)日：2008-06-26

申请号：US11643100

申请日：2006-12-21

Applicant: Hossein Amidi

Inventor： Hossein Amidi

IPC: H03M13/00

CPC classification number: H03M13/03 ,  H03M13/09 ,  H03M13/091 ,  H03M13/3776

Abstract: A memory module having error detection and correction mechanisms is disclosed. The memory module includes a plurality of memory devices arranged in an array and a buffer device connected to the memory devices. The buffer device includes a register module for synchronizing and buffering a plurality of input signals to the memory devices, an error detection module for detecting errors of the input signals, and a transmission memory for storing a copy of the input signals and transmitting the stored copy of the input signals as an output signal.

Abstract translation: 公开了一种具有错误检测和校正机制的存储器模块。 存储器模块包括布置在阵列中的多个存储器件和连接到存储器件的缓冲器件。 该缓冲装置包括用于同步并缓冲多个输入信号到存储装置的寄存器模块，用于检测输入信号的错误的错误检测模块，以及用于存储输入信号的副本并发送存储的副本 的输入信号作为输出信号。

公开(公告)号：US20080123305A1

公开(公告)日：2008-05-29

申请号：US11605809

申请日：2006-11-28

Applicant: Hossein Amidi ,  Satyadev Kolli

Inventor： Hossein Amidi ,  Satyadev Kolli

IPC: H05K1/14

CPC classification number: H05K1/181 ,  G11C5/02 ,  G11C5/04 ,  G11C8/16 ,  H05K1/117 ,  H05K2201/09972 ,  H05K2201/10159 ,  Y02P70/611

Abstract: A dual-channel memory module for use in computing devices is disclosed. The memory module can include a substrate having a base portion, a first connector portion, and a second connector portion spaced apart and electrically insulated from the first connector portion. A first set of memory devices is disposed on the base portion and in electrical communication with the first connector portion, and a second set of memory devices is disposed on the base portion and in electrical communication with the second connector portion. The first and second sets of memory devices are independent of each other.

Abstract translation: 公开了一种用于计算设备的双通道内存模块。 存储器模块可以包括具有基座部分，第一连接器部分和与第一连接器部分间隔开并与之电绝缘的第二连接器部分的基板。 第一组存储器件设置在基座部分上并且与第一连接器部分电连通，并且第二组存储器件设置在基座部分上并与第二连接器部分电连通。 第一组和第二组存储器件彼此独立。

公开(公告)号：US20060118950A1

公开(公告)日：2006-06-08

申请号：US10613398

申请日：2003-07-03

Applicant: Hossein Amidi ,  Kelvin Marino ,  Satyadey Kolli

Inventor： Hossein Amidi ,  Kelvin Marino ,  Satyadey Kolli

IPC: H01L23/34

CPC classification number: G11C5/04 ,  H05K1/0286 ,  H05K1/117

Abstract: A memory module has a printed circuit board with connector pins. Several memory devices are mounted on the printed circuit board. An electrical circuit connects the memory devices to the connector pins such that the connector pins have multiple functionality based on the architecture of the memory devices used.

Abstract translation: 存储器模块具有带有连接器引脚的印刷电路板。 几个存储器件安装在印刷电路板上。 电路将存储器件连接到连接器引脚，使得连接器引脚具有基于所使用的存储器件的架构的多种功能。

公开(公告)号：US20250077089A1

公开(公告)日：2025-03-06

申请号：US18239376

申请日：2023-08-29

Applicant: SMART Modular Technologies, Inc.

Inventor： Andrew Mills ,  Torry Steed

IPC: G06F3/06

Abstract: Systems and methods for memory snapshots are disclosed. In particular, a memory device may include a volatile section and a backup persistent storage section. A snapshot manager circuit is positioned between a host control circuit or central processors. This snapshot manager circuit acts as a memory virtualization layer within the memory device and may use a redirect on write type command to put a snapshot of actively changed memory to a reserved memory area in the volatile section. A background function may copy the snapshots to the persistent storage section. Because the snapshot manager circuit is in the hardware memory access layers of the memory device, operation of the application is not interrupted or paused to access the specific memory sections. Further, snapshots are more readily available in the memory used by the host control circuit.

公开(公告)号：US11561739B1

公开(公告)日：2023-01-24

申请号：US16889729

申请日：2020-06-01

Applicant: SMART Modular Technologies, Inc.

Inventor： Kelvin Alberto Marino

IPC: G06F3/06 ,  G06F1/30 ,  G06F11/14

Abstract: A persistent memory unit for a computer system where the memory unit can detect a catastrophic event and automatically backup volatile memory into non-volatile memory. The memory unit can operate with a limited number of power inputs and detect the loss of power and then initiate a backup after the volatile memory of the memory unit has entered a stable self-refresh mode. The memory unit uses an on-board power management interface controller capable of redistributing power from an input power line and generating different power levels for different components on the memory unit.

公开(公告)号：US10573354B2

公开(公告)日：2020-02-25

申请号：US15273385

申请日：2016-09-22

Applicant: SMART Modular Technologies, Inc.

Inventor： Satyanarayan Shivkumar Iyer ,  Robert S. Pauley, Jr.

IPC: G06F12/00 ,  G11C7/00 ,  G06F13/00 ,  G06F13/28 ,  G06F3/06

Abstract: Approaches, techniques, and mechanisms are disclosed for manufacturing and operating high density memory systems. The high density memory systems can increase the amount of memory available to a computing system by allowing the connection of multiple memory modules into a single memory interface on a motherboard via a memory adapter as described herein.

公开(公告)号：US09204550B2

公开(公告)日：2015-12-01

申请号：US13633074

申请日：2012-10-01

Applicant: SMART Modular Technologies, Inc.

Inventor： Victor Mahran ,  Robert S. Pauley, Jr.

IPC: G06F1/16 ,  H05K5/00 ,  H05K7/00 ,  H05K7/20 ,  H01L23/48 ,  H01R12/00 ,  H05K1/14 ,  H05K7/14 ,  H05K1/02 ,  G06F1/20 ,  G11C5/02

CPC classification number: G06F1/185 ,  G06F1/20 ,  G11C5/025 ,  H05K1/0209 ,  H05K1/144 ,  H05K1/145 ,  H05K7/1431 ,  H05K2201/042 ,  H05K2201/10159 ,  H05K2201/10303 ,  H05K2201/10378 ,  H05K2201/10409 ,  Y10T29/4913

Abstract: A method of manufacture of an enhanced capacity memory system includes: providing a dual in-line memory module carrier having a memory module and an integrated memory buffer coupled to the memory module; coupling a memory expansion board, having a supplementary memory module, to the dual in-line memory module carrier including attaching a bridge transposer; and providing a system interface connector coupled to the integrated memory buffer and the bridge transposer for controlling the memory module, the supplementary memory module, or a combination thereof.

Abstract translation: 一种制造增强容量存储器系统的方法包括：提供具有存储器模块和耦合到存储器模块的集成存储器缓冲器的双列直插存储器模块载体; 将具有辅助存储器模块的存储器扩展板耦合到双列直插式存储器模块载体，包括附接桥式变压器; 并且提供耦合到集成存储器缓冲器的系统接口连接器和用于控制存储器模块，辅助存储器模块或其组合的桥接转换器。

公开(公告)号：US08990489B2

公开(公告)日：2015-03-24

申请号：US13568694

申请日：2012-08-07

Applicant: Hossein Amidi ,  Kelvin A. Marino ,  Satyadev Kolli

Inventor： Hossein Amidi ,  Kelvin A. Marino ,  Satyadev Kolli

IPC: G06F12/00 ,  G11C8/00 ,  G11C8/12 ,  G11C5/04 ,  G11C7/10 ,  G11C7/22

CPC classification number: G11C8/12 ,  G11C5/04 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222

Abstract: A transparent four rank memory module has a front side and a back side. The front side has a third memory rank stacked on a first memory rank. The back side has a fourth memory rank stacked on a second memory rank. An emulator coupled to the memory module activates and controls one individual memory rank from either the first memory rank, the second memory rank, the third memory rank, or the fourth memory rank based on the signals received from a memory controller.

Abstract translation: 透明的四级存储器模块具有前侧和后侧。 前侧具有堆叠在第一存储器等级上的第三存储器级。 背面具有堆叠在第二存储器等级上的第四存储器级。 耦合到存储器模块的仿真器基于从存储器控制器接收的信号来激活并控制来自第一存储器级，第二存储器级，第三存储器级或第四存储器级的一个单独的存储器级。

公开(公告)号：US08644105B2

公开(公告)日：2014-02-04

申请号：US12770576

申请日：2010-04-29

Applicant: Mike H. Amidi ,  Satyadev Kolli

Inventor： Mike H. Amidi ,  Satyadev Kolli

IPC: G11C8/00

CPC classification number: G11C5/143 ,  G11C7/22 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4074 ,  G11C11/4076 ,  G11C2211/4067

Abstract: A system, method and apparatus for clock and power fault detection for a memory module is provided. In one embodiment, a system is provided. The system includes a voltage detection circuit and a clock detection circuit. The system further includes a controller coupled to the voltage detection circuit and the clock detection circuit. The system also includes a memory control state machine coupled to the controller. The system includes volatile memory coupled to the memory control state machine. The system further includes a battery and battery regulation circuitry coupled to the controller and the memory control state machine. The battery, battery regulation circuitry, volatile memory, memory control state machine, controller, clock detection circuit and voltage detection circuit are all collectively included in a unitary memory module.

Abstract translation: 提供了一种用于存储器模块的时钟和电源故障检测的系统，方法和装置。 在一个实施例中，提供了一种系统。 该系统包括电压检测电路和时钟检测电路。 该系统还包括耦合到电压检测电路和时钟检测电路的控制器。 该系统还包括耦合到控制器的存储器控​​制状态机。 该系统包括耦合到存储器控制状态机的易失性存储器。 该系统还包括耦合到控制器和存储器控制状态机的电池和电池调节电路。 电池，电池调节电路，易失性存储器，存储器控制状态机，控制器，时钟检测电路和电压检测电路都集成在一体式存储器模块中。