公开(公告)号：US08225503B2

公开(公告)日：2012-07-24

申请号：US12163252

申请日：2008-06-27

Applicant: Takashi Kariya ,  Toshiki Furutani

Inventor： Takashi Kariya ,  Toshiki Furutani

IPC: H05K3/10

CPC classification number: H05K3/428 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/12105 ,  H01L2224/26175 ,  H01L2224/73204 ,  H01L2224/83132 ,  H01L2224/83192 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01093 ,  H01L2924/14 ,  H05K1/187 ,  H05K3/205 ,  H05K3/243 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0341 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/0959 ,  H05K2201/0969 ,  H05K2201/09918 ,  H05K2201/10674 ,  H05K2203/0361 ,  H05K2203/063 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/05599

Abstract: A method for manufacturing a board with a built-in electronic element, includes providing a support substrate including a support base and a metal foil, forming a protective film made of a metal material on the metal foil of the support substrate, forming a conductive pattern made of a metal material on the protective film by an additive method, placing an electronic element on the support substrate with the conductive pattern such that a surface of the electronic element where a circuit is formed faces the conductive pattern, covering the electronic element with an insulative resin, etching away the metal foil using a first etching solution such that the protective film is not dissolved by the first etching solution or that the protective film has an etching speed which is slower than an etching speed of the metal foil, and electrically connecting terminals of the electronic element and a part of the conductive pattern.

Abstract translation: 一种用于制造具有内置电子元件的板的方法，包括提供包括支撑基底和金属箔的支撑基板，在支撑基板的金属箔上形成由金属材料制成的保护膜，形成导电图案 通过添加方法在保护膜上由金属材料制成，将电子元件放置在具有导电图案的支撑基板上，使得形成电路的电子元件的表面面向导电图案，用电子元件覆盖电子元件 绝缘树脂，使用第一蚀刻溶液蚀刻掉金属箔，使得保护膜不被第一蚀刻溶液溶解，或者保护膜具有比金属箔的蚀刻速度慢的蚀刻速度，并且电连接 电子元件的端子和导电图案的一部分。

公开(公告)号：US20120152598A1

公开(公告)日：2012-06-21

申请号：US13326016

申请日：2011-12-14

Applicant: Erina YAMADA ,  Kazunaga Higo ,  Hironori Sato

Inventor： Erina YAMADA ,  Kazunaga Higo ,  Hironori Sato

IPC: H05K1/09 ,  B23K31/02 ,  B23K1/20 ,  H05K3/10

CPC classification number: B23K1/0016 ,  B23K2101/42 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2924/14 ,  H05K3/3473 ,  H05K3/3478 ,  H05K2201/0341 ,  H05K2203/041 ,  H05K2203/043 ,  H05K2203/054 ,  H05K2203/0574 ,  H05K2203/1476 ,  H01L2924/00

Abstract: Disclosed is a method for manufacturing a wiring board including a conductor layer, a solder resist layer laminated on the conductor layer, and a conductor post to be electrically connected to a conductor layer which is disposed in a lower portion of a through-hole provided in the solder resist layer, the method including a through-hole boring process of boring the through-hole in the solder resist layer containing a thermosetting resin to expose the conductor layer within the through-hole; a first conductor part forming process of forming a first conductor part composed mainly of copper within the through-hole; and a second conductor part forming process of forming a second conductor part composed mainly of tin, copper, or a solder on the first conductor part, in this order.

Abstract translation: 公开了一种制造布线板的方法，该布线板包括导体层，层压在导体层上的阻焊层，以及导体柱，该导体柱与导体层电连接，该导体层设置在设置在导体层中的通孔的下部 阻焊层，该方法包括在包含热固性树脂的阻焊层中钻通孔的通孔钻孔工艺，以暴露通孔内的导体层; 在所述通孔内形成主要由铜构成的第一导体部的第一导体部形成工序; 以及在第一导体部分上形成主要由锡，铜或焊料组成的第二导体部分的第二导体部分形成工艺。

公开(公告)号：US08018063B2

公开(公告)日：2011-09-13

申请号：US12610211

申请日：2009-10-30

Applicant: Daewoong Suh ,  Stephen E. Lehman, Jr. ,  Mukul Renavikar

Inventor： Daewoong Suh ,  Stephen E. Lehman, Jr. ,  Mukul Renavikar

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H05K3/3484 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/11 ,  H01L2224/11822 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/136 ,  H01L2224/81011 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H05K3/244 ,  H05K3/3436 ,  H05K2201/0215 ,  H05K2201/0341 ,  H05K2203/0435 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A microelectronic assembly and method for fabricating the same are described. In an example, a microelectronic assembly includes a microelectronic device having a surface with one or more areas to receive one or more solder balls, the one or more areas having a surface finish comprising Ni. A solder material comprising Cu, such as flux or paste, is applied to the Ni surface finish and one or more solder balls are coupled to the microelectronic device by a reflow process that forms a solder joint between the one or more solder balls, the solder material comprising Cu, and the one or more areas having a surface finish comprising Ni.

Abstract translation: 描述了一种微电子组件及其制造方法。 在一个示例中，微电子组件包括具有一个或多个区域以接收一个或多个焊球的表面的微电子器件，所述一个或多个区域具有包括Ni的表面光洁度。 将包含Cu的焊料材料（例如焊剂或糊料）施加到Ni表面光洁度上，并且一个或多个焊球通过在一个或多个焊球之间形成焊料接头的回流工艺耦合到微电子器件，焊料 包含Cu的材料，并且所述一个或多个区域具有包括Ni的表面光洁度。

公开(公告)号：US20100044848A1

公开(公告)日：2010-02-25

申请号：US12610211

申请日：2009-10-30

Applicant: Daewoong Suh ,  Stephen E. Lehman, JR. ,  Mukul Renavikar

Inventor： Daewoong Suh ,  Stephen E. Lehman, JR. ,  Mukul Renavikar

IPC: H01L23/485

CPC classification number: H05K3/3484 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/11 ,  H01L2224/11822 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/136 ,  H01L2224/81011 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H05K3/244 ,  H05K3/3436 ,  H05K2201/0215 ,  H05K2201/0341 ,  H05K2203/0435 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A microelectronic assembly and method for fabricating the same are described. In an example, a microelectronic assembly includes a microelectronic device having a surface with one or more areas to receive one or more solder balls, the one or more areas having a surface finish comprising Ni. A solder material comprising Cu, such as flux or paste, is applied to the Ni surface finish and one or more solder balls are coupled to the microelectronic device by a reflow process that forms a solder joint between the one or more solder balls, the solder material comprising Cu, and the one or more areas having a surface finish comprising Ni.

Abstract translation: 描述了一种微电子组件及其制造方法。 在一个示例中，微电子组件包括具有一个或多个区域以接收一个或多个焊球的表面的微电子器件，所述一个或多个区域具有包括Ni的表面光洁度。 将包含Cu的焊料材料（例如焊剂或糊料）施加到Ni表面光洁度上，并且一个或多个焊球通过在一个或多个焊球之间形成焊料接头的回流工艺耦合到微电子器件，焊料 包含Cu的材料，并且所述一个或多个区域具有包括Ni的表面光洁度。

公开(公告)号：US20090114345A1

公开(公告)日：2009-05-07

申请号：US12289473

申请日：2008-10-28

Applicant: Hiroki Nakayama ,  Juntarou Mikami

Inventor： Hiroki Nakayama ,  Juntarou Mikami

IPC: B29C63/00

CPC classification number: H01L21/4846 ,  H01L2224/48247 ,  H05K1/09 ,  H05K3/062 ,  H05K3/284 ,  H05K2201/0338 ,  H05K2201/0341 ,  H05K2203/1184 ,  Y10T156/11

Abstract: A method for manufacturing a substrate for mounting a semiconductor element includes: a step for forming a predetermined resist pattern by affixing resists on both faces of a base material including a metallic thin plate and using the resist of one of the faces as a masking for plating; a step for performing an etching of a predetermined position on a base material exposed from the resist pattern; a step for forming a plating layer having at least three layers including a lower, a middle, and an upper layer on the etched base material; a step for separating the resists affixed to both faces of a base material; and a step for performing an etching of the middle plating layer to make the middle plating layer narrower than the upper and lower plating layers.

Abstract translation: 一种用于安装半导体元件的基板的制造方法包括：通过在包括金属薄板的基材的两面上固定抗蚀剂并使用其中一个表面的抗蚀剂作为电镀掩模来形成预定抗蚀剂图案的步骤 ; 在从抗蚀剂图案曝光的基材上进行预定位置的蚀刻的步骤; 在蚀刻后的基材上形成具有下层，中层和上层的至少3层的镀层的工序; 分离固定在基材两面上的抗蚀剂的工序; 以及进行中间镀层的蚀刻以使中间镀层比上，下镀层窄的工序。

公开(公告)号：US07312403B2

公开(公告)日：2007-12-25

申请号：US11231746

申请日：2005-09-22

Applicant: Kouki Yamamoto

Inventor： Kouki Yamamoto

IPC: H05K1/16

CPC classification number: H05K3/3442 ,  H05K1/111 ,  H05K3/243 ,  H05K3/244 ,  H05K3/284 ,  H05K3/4015 ,  H05K2201/0209 ,  H05K2201/0341 ,  H05K2201/0347 ,  H05K2201/09481 ,  H05K2201/0959 ,  H05K2201/09736 ,  H05K2201/10636 ,  Y02P70/611 ,  Y02P70/613

Abstract: A circuit component mounting device includes a resin substrate, vias, a circuit component composed of a main body and electrode portions, a solder, and an insulative sealing resin that covers the circuit component and the solder. The device further includes a base metal pattern which covers parts of the principal face of the resin substrate where the vias are exposed and is composed of a Cu layer and a Ni layer and a copper plated pattern which is provided on the base metal pattern and is composed of a Cu layer, a Ni layer, and an Au layer. The circuit component is provided on the copper plated pattern. The solder allows the copper plated pattern and the circuit component to adhere to each other.

Abstract translation: 电路部件安装装置包括树脂基板，通孔，由主体和电极部分组成的电路部件，焊料和覆盖电路部件和焊料的绝缘密封树脂。 该装置还包括基体金属图案，其覆盖树脂基板的主要面的部分，其中通孔露出，并且由Cu层和Ni层构成，并且镀铜图案设置在基底金属图案上，并且是 由Cu层，Ni层和Au层构成。 电路元件设置在镀铜图案上。 焊料允许镀铜图案和电路部件彼此粘附。

公开(公告)号：US5274195A

公开(公告)日：1993-12-28

申请号：US891700

申请日：1992-06-02

Applicant: Davis W. Murphy ,  Dennis A. Bonnette ,  Thomas H. Stearns

Inventor： Davis W. Murphy ,  Dennis A. Bonnette ,  Thomas H. Stearns

IPC: H05K1/00 ,  H05K3/06 ,  H05K3/28 ,  H05K3/40 ,  H01B7/08

CPC classification number: H05K3/06 ,  H05K3/4092 ,  H05K1/0393 ,  H05K2201/0341 ,  H05K2201/0367 ,  H05K2201/09736 ,  H05K2203/0353 ,  H05K2203/0369 ,  H05K2203/0384 ,  H05K3/281 ,  Y10T29/49156 ,  Y10T29/49218 ,  Y10T29/49222 ,  Y10T428/1291

Abstract: A laminate comprising metal layers separated by an etchant barrier to control depth of etching of the laminate, the barrier being etchable by an etchant which is not an etchant for the layers. A cable incorporating such a laminate and having relatively flexible conductors integral with relatively rigid terminals. A method of making such a cable, using the laminate, by selectively etching the layers down to the barrier to form the conductors and terminals, stripping the barrier and laminating the conductor with an insulating material preferably extending over at least a portion of the terminals to reinforce the conductor terminal transition and a cable when made of such a method.

Abstract translation: 包括由蚀刻剂屏障分隔的金属层以控制层压体的蚀刻深度的层压体，所述阻挡层可被不是所述层的蚀刻剂的蚀刻剂蚀刻。 一种包含这种层压板并且具有与相对刚性端子成一体的相对柔性导体的电缆。 通过选择性地将这些层选择性地蚀刻到屏障以形成导体和端子，制造这种电缆的方法，剥离屏障并且用优选在端子的至少一部分上延伸的绝缘材料层压导体至 加强导线端子的过渡和使用这种方法制成的电缆。

公开(公告)号：US12089331B2

公开(公告)日：2024-09-10

申请号：US17314131

申请日：2021-05-07

Applicant: Aplus Semiconductor Technologies Co., Ltd.

Inventor： Cheng-Neng Chen ,  Sui-Ho Tsai ,  Yun-Nan Wang ,  Chiao-Hui Wang

IPC: H05K1/14 ,  C23C14/34 ,  C23C14/58 ,  C23C18/16 ,  C23C28/02 ,  C25D5/02 ,  C25D5/10 ,  G03F7/004 ,  G03F7/20 ,  H05K1/11

CPC classification number: H05K1/147 ,  C23C14/34 ,  C23C14/5873 ,  C23C18/1637 ,  C23C28/023 ,  C25D5/022 ,  C25D5/10 ,  G03F7/0041 ,  G03F7/2016 ,  H05K1/11 ,  H05K2201/032 ,  H05K2201/0338 ,  H05K2201/0341

Abstract: A metal circuit structure based on a flexible printed circuit (FPC) contains: a substrate, a first metal layer attached on the substrate, a second metal layer formed on the first metal layer, and an intermediate layer defined between the first metal layer and the second metal layer. A first surface of the intermediate layer is connected with the first metal layer, and a second surface of the intermediate layer is connected with the second metal layer. The intermediate layer is made of a first material, the second metal layer is made of a second material, and the first material of the intermediate layer does not act with the second material of the second metal layer.

公开(公告)号：US11908768B2

公开(公告)日：2024-02-20

申请号：US17671635

申请日：2022-02-15

Applicant: MITSUBISHI MATERIALS CORPORATION

Inventor： Ryohei Yumoto ,  Tomoya Oohiraki ,  Takeshi Kitahara ,  Yoshiyuki Nagatomo

IPC: H05K1/09 ,  H05K1/18 ,  H05K3/22 ,  H01L21/52 ,  H01L23/12 ,  H01L23/367 ,  H01L23/473 ,  H01L23/373 ,  H01L21/48 ,  H05K3/00 ,  H05K3/02

CPC classification number: H01L23/3735 ,  H01L21/4857 ,  H05K1/09 ,  H05K3/0097 ,  H05K3/022 ,  H05K3/0052 ,  H05K2201/0341 ,  H05K2201/0379 ,  H05K2203/068

Abstract: Forming aluminum circuit layers forming an aluminum circuit layers on one surface of a ceramic substrate and forming copper circuit layers are included. The copper circuit layers are formed by laminating copper boards for the circuit layers on the respective aluminum circuit layers, arranging the laminate between a pair of support boards having a convex curved surface at least on one surface so as to face to each other, moving the support boards in a facing direction to press the laminate in a lamination direction, and heating in this pressing state so that the copper boards for the circuit layers are bonded on the aluminum circuit layers respectively by solid phase diffusion. In the step of forming the copper circuit layers, the support boards are arranged so that either one of the convex curved surface is in contact with the adjacent copper boards for the circuit layers in the laminate.

公开(公告)号：US20180368265A1

公开(公告)日：2018-12-20

申请号：US16121822

申请日：2018-09-05

Applicant: Avary Holding (Shenzhen) Co., Limited. ,  HongQiSheng Precision Electronics(QinHuangDao) Co. , Ltd.

Inventor： LEI ZHOU ,  RUI-WU LIU ,  QIONG ZHOU

IPC: H05K1/18 ,  H05K1/03 ,  H05K3/06 ,  H05K3/18 ,  H05K1/09

CPC classification number: H05K1/189 ,  H05K1/032 ,  H05K1/09 ,  H05K3/064 ,  H05K3/108 ,  H05K3/188 ,  H05K3/244 ,  H05K2201/0341 ,  H05K2201/0769 ,  H05K2203/0588 ,  H05K2203/072 ,  H05K2203/0723 ,  Y10T29/49155

Abstract: A flexible printed circuit board with reduced ion migration from signal-carrying elements which are coated against corrosion includes an insulating layer, a wiring area, a copper electroplating layer, a nickel electroplating layer, a cover film, and a gold chemical-plating layer. The wiring area is formed on the insulating layer. The copper electroplating layer formed on the wiring area has a first portion and a second portion. The nickel electroplating layer is formed on at least the first portion and exposes sidewalls of the first portion. The cover film is formed on the second portion and fills in gaps of the copper electroplating layer. The gold chemical-plating layer is formed on top surface of the nickel electroplating layer and the sidewalls of the first portion.