公开(公告)号：US09204532B2

公开(公告)日：2015-12-01

申请号：US14113582

申请日：2013-07-31

Applicant: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD

Inventor： Peng Du ,  Ming hung Shih ,  Jiali Jiang

IPC: G02F1/1345 ,  H05K1/02 ,  H05K1/16

CPC classification number: H05K1/025 ,  G02F1/1345 ,  H05K1/0248 ,  H05K1/162 ,  H05K2201/0326 ,  H05K2201/0391 ,  H05K2201/09227 ,  H05K2201/09763 ,  H05K2201/10136

Abstract: A fanout line structure of an array substrate includes first fanout lines arranged on a fanout area of the array substrate, and second fanout lines arranged on the fanout area of the array substrate. A second conducting film is arranged at a bottom of the second fanout line, a second capacitor is formed between the second conducting film and a first conducting film of the second fanout line, the second capacitor is used to reduce an impedance difference between the fanout lines. Capacitance value of the second capacitor is dependent on an overlapping area between the second conducting film and the first conducting film.

Abstract translation: 阵列基板的扇出线结构包括布置在阵列基板的扇出区域上的第一扇出线和布置在阵列基板的扇出区域上的第二扇出线。 第二导电膜布置在第二扇出线的底部，第二电容器形成在第二导电膜和第二扇出线的第一导电膜之间，第二电容用于降低扇出线之间的阻抗差 。 第二电容器的电容值取决于第二导电膜和第一导电膜之间的重叠面积。

公开(公告)号：US20150296607A1

公开(公告)日：2015-10-15

申请号：US14251227

申请日：2014-04-11

Applicant: APPLE INC.

Inventor： Henry H. Yang ,  Matthew E. Last ,  Tongbi T. Jiang

IPC: H05K1/02 ,  H05K1/09 ,  H05K1/03 ,  G01B7/16 ,  H05K1/18

CPC classification number: H05K1/028 ,  G01L1/205 ,  G01L1/2287 ,  G06F3/00 ,  G06K9/00006 ,  H05K1/167 ,  H05K2201/0154 ,  H05K2201/0391 ,  H05K2201/09263 ,  H05K2201/10151

Abstract: An electronic device may be provided with a flexible printed circuit. The flexible printed circuit may have layers of metal and dielectric. Strain gauge resistors may be formed from a strain gauge metal such as constantan. The strain gauge metal may be formed within the flexible printed circuit layers. A strain gauge may include strain gauge circuitry coupled to a strain gauge bridge circuit. Strain gauge resistors for the bridge circuit may be formed from traces that follow parallel meandering paths in the flexible printed circuit layers. A component such as a fingerprint sensor may overlap the strain gauge resistors. Strain gauge resistors may be formed in different overlapping metal layers in the flexible printed circuit layers or may be formed from the same metal layer. Electroplating techniques may be used to form metal traces to which solder balls or wire bonds are coupled.

Abstract translation: 电子设备可以设置有柔性印刷电路。 柔性印刷电路可以具有金属和电介质层。 应变计电阻器可以由诸如康铜的应变计金属形成。 应变计金属可以形成在柔性印刷电路层内。 应变仪可以包括耦合到应变仪桥接电路的应变仪电路。 用于桥接电路的应变计电阻器可以由沿着柔性印刷电路层中的平行弯曲路径的迹线形成。 诸如指纹传感器的组件可能与应变计电阻重叠。 应变计电阻器可以形成在柔性印刷电路层中的不同重叠的金属层中，或者可以由相同的金属层形成。 可以使用电镀技术来形成连接焊球或引线键的金属迹线。

公开(公告)号：US20150136458A1

公开(公告)日：2015-05-21

申请号：US14182206

申请日：2014-02-17

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Eun Ju Yang ,  Gyu Seok Kim ,  Suk Jin Ham ,  Se Yoon Park ,  Jin Uk Cha ,  Hee Suk Chung ,  Mi Yang Kim

IPC: H05K1/09 ,  H05K3/06 ,  C23C14/34 ,  H05K1/03 ,  C23F4/04

CPC classification number: H05K1/09 ,  C23C14/185 ,  C23C14/34 ,  C23C14/5833 ,  C23F4/00 ,  C23F4/04 ,  H05K1/03 ,  H05K1/0306 ,  H05K3/027 ,  H05K3/06 ,  H05K3/16 ,  H05K3/388 ,  H05K2201/0391 ,  H05K2203/092

Abstract: Disclosed herein are a printed circuit board and a method of manufacturing the same. In detail, according to a preferred embodiment of the present invention, the printed circuit board includes: an insulating layer; and a metal layer formed on the insulating layer, wherein in the metal layer, a ratio occupied by crystal orientations of (110) and (112) is 20 to 80%. By doing so, the preferred embodiment of the present invention provides a printed circuit board including the metal layer having different crystal orientations to minimize factors of hindering electrical characteristics such as electric conductivity and improve isotropy of mechanical properties and a method of manufacturing the printed circuit board.

Abstract translation: 这里公开了一种印刷电路板及其制造方法。 具体地，根据本发明的优选实施例，印刷电路板包括：绝缘层; 以及形成在所述绝缘层上的金属层，其中在所述金属层中，（110）和（112）的晶体取向所占的比例为20〜80％。 通过这样做，本发明的优选实施例提供了一种印刷电路板，其包括具有不同晶体取向的金属层，以最小化妨碍诸如导电性的电特性的因素，并改善机械性能的各向同性和制造印刷电路板的方法 。

公开(公告)号：US20150116963A1

公开(公告)日：2015-04-30

申请号：US14520481

申请日：2014-10-22

Applicant: Koji Hachiya ,  Tomoyoshi Kobayashi ,  Koichi Nakabayashi

Inventor： Koji Hachiya ,  Tomoyoshi Kobayashi ,  Koichi Nakabayashi

IPC: H05K1/16 ,  H05K1/18

CPC classification number: H05K1/165 ,  H05K1/181 ,  H05K2201/0355 ,  H05K2201/0391 ,  H05K2201/086 ,  H05K2201/09063

Abstract: A coil-integrated printed circuit board includes: a first outer layer which includes a first outer thick electric conductor made of a thick metallic foil and a first outer thin electric conductor made of a thin metallic foil having a thickness smaller than that of the first outer thick electric conductor, and which is exposed to an outside; and a first inner layer which includes an inner thick electric conductor made of a thick metallic foil, and which is not exposed to the outside. Coil patterns are respectively formed by the first outer thick electric conductor and the inner thick electric conductor. A first electronic component is surface-mounted on the first outer thin electric conductor provided on the outer layer.

Abstract translation: 线圈集成印刷电路板包括：第一外层，其包括由厚金属箔制成的第一外部厚电导体和由薄金属箔制成的第一外部薄导电体，该薄金属箔的厚度小于第一外部厚度 厚电导体，暴露于外部; 以及第一内层，其包括由厚金属箔制成且不暴露于外部的内部厚电导体。 线圈图案分别由第一外部厚电导体和内部厚电导体形成。 第一电子部件被表面安装在设置在外层上的第一外部薄导电导体上。

公开(公告)号：US08921704B2

公开(公告)日：2014-12-30

申请号：US13850315

申请日：2013-03-26

Applicant: Todd Mathew Spath

Inventor： Todd Mathew Spath

IPC: H05K1/09 ,  H05K3/10

CPC classification number: H05K1/09 ,  H05K3/02 ,  H05K2201/0108 ,  H05K2201/0329 ,  H05K2201/0391 ,  H05K2201/09909 ,  H05K2203/1142 ,  Y10T29/49162

Abstract: A patterned conductive structure includes a transparent substrate having a substrate surface. A conductive polymer layer is formed on the substrate surface. The conductive polymer layer has electrically conductive areas and deactivated areas that are less electrically conductive than the conductive areas. The conductive areas and the deactivated areas form a conductive pattern in the polymer layer. One or more transparent dielectric patches that are less electrically conductive than the deactivated areas are formed over at least a portion of one or more deactivated areas and one or more conductive wires are formed over at least one of the dielectric patches.

Abstract translation: 图案化导电结构包括具有基板表面的透明基板。 在基板表面上形成导电聚合物层。 导电聚合物层具有比导电区域导电性更差的导电区域和去活化区域。 导电区域和去活化区域在聚合物层中形成导电图案。 在一个或多个去活化区域的至少一部分上形成一个或多个比非去活化区域更不导电的透明电介质贴片，并且在至少一个电介质贴片上形成一个或多个导线。

公开(公告)号：US08790504B2

公开(公告)日：2014-07-29

申请号：US12797905

申请日：2010-06-10

Applicant: Kotaro Kodani

Inventor： Kotaro Kodani

IPC: C25D5/02 ,  C25D1/00

CPC classification number: C25D1/003 ,  C25D5/022 ,  C25D5/14 ,  H01L21/4857 ,  H01L23/3675 ,  H01L23/49822 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/3511 ,  H05K3/205 ,  H05K3/4682 ,  H05K2201/0391 ,  H05K2201/09736 ,  H05K2201/10371 ,  H05K2201/10674 ,  H05K2203/0361 ,  H01L2224/0401

Abstract: There is provided a method of manufacturing a wiring substrate. The method includes: (a) forming a first resist layer having first openings therein on a first surface of a support plate, forming first plated films in the first openings by an electrolytic plating method, and removing the first resist layer; (b) forming a second resist layer having second openings therein on the first surface of the support plate, forming second plated films in the second openings by an electrolytic plating method, and removing the second resist layer; (c) forming a wiring layer and an insulating layer such that the wiring layer is electrically connected to the first and second plated films; and (d) removing the support plate to expose the first and second plated films.

Abstract translation: 提供一种制造布线基板的方法。 该方法包括：（a）在支撑板的第一表面上形成具有第一开口的第一抗蚀剂层，通过电解电镀法在第一开口中形成第一镀膜，并除去第一抗蚀剂层; （b）在支撑板的第一表面上形成具有第二开口的第二抗蚀剂层，通过电解电镀方法在第二开口中形成第二镀膜，并除去第二抗蚀剂层; （c）形成布线层和绝缘层，使得布线层电连接到第一和第二镀膜; 和（d）移除支撑板以露出第一和第二镀膜。

公开(公告)号：US08450623B2

公开(公告)日：2013-05-28

申请号：US12785725

申请日：2010-05-24

Applicant: Tzyy-Jang Tseng ,  Shu-Sheng Chiang ,  Tsung-Yuan Chen

Inventor： Tzyy-Jang Tseng ,  Shu-Sheng Chiang ,  Tsung-Yuan Chen

IPC: H05K1/11

CPC classification number: H05K3/465 ,  C23C18/1612 ,  C23C18/1651 ,  C23C18/1653 ,  C23C18/1689 ,  H05K1/0265 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/045 ,  H05K3/107 ,  H05K2201/0391 ,  H05K2201/09509 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A circuit board includes a circuit substrate, a dielectric layer, and a patterned circuit structure. The dielectric layer covers a first surface and at least a first circuit of the circuit substrate. The dielectric layer has a second surface, at least a blind via extending from the second surface to the first circuit, a first intaglio pattern, and a second intaglio pattern. The patterned circuit structure includes at least a second circuit and a plurality of third circuits. The second circuit is disposed in the first intaglio pattern. The third circuits are disposed in the second intaglio pattern and the blind via. Each third circuit has a first conductive layer, a second conductive layer, and a barrier layer. The first conductive layer is located between the barrier layer and the second intaglio pattern and between the barrier layer and the blind via. The second conductive layer covers the barrier layer.

Abstract translation: 电路板包括电路基板，电介质层和图案化电路结构。 电介质层覆盖电路基板的第一表面和至少第一电路。 电介质层具有第二表面，至少从第二表面延伸到第一电路的盲孔，第一凹版图案和第二凹版图案。 图案化电路结构至少包括第二电路和多个第三电路。 第二电路设置在第一凹版图案中。 第三电路设置在第二凹版图案和盲通孔中。 每个第三电路具有第一导电层，第二导电层和阻挡层。 第一导电层位于阻挡层和第二凹版图案之间以及阻挡层和盲孔之间。 第二导电层覆盖阻挡层。

公开(公告)号：US20120200346A1

公开(公告)日：2012-08-09

申请号：US13448787

申请日：2012-04-17

Applicant: Moises Cases ,  Tae Hong Kim ,  Rohan U. Mandrekar ,  Nusrat I. Sherali

Inventor： Moises Cases ,  Tae Hong Kim ,  Rohan U. Mandrekar ,  Nusrat I. Sherali

IPC: H02J3/10 ,  H05K3/00

CPC classification number: H05K3/0094 ,  H05K1/0234 ,  H05K1/0242 ,  H05K1/0251 ,  H05K1/09 ,  H05K1/167 ,  H05K3/0047 ,  H05K3/244 ,  H05K3/429 ,  H05K2201/0391 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T156/1057 ,  Y10T428/12528

Abstract: Example multi-layer printed circuit boards (‘PCBs’) are described as well as methods of making and using such PCBs that include layers of laminate; at least one via hole traversing the layers of laminate, and a via conductor contained within the via hole, the via conductor comprising a used portion and an unused portion, the via conductor comprising copper coated with a metal having a conductivity lower than the conductivity of copper.

公开(公告)号：US20110261847A1

公开(公告)日：2011-10-27

申请号：US12768679

申请日：2010-04-27

Applicant: HSI-YAN CHOU

Inventor： HSI-YAN CHOU

IPC: H01S5/00 ,  H01L33/46

CPC classification number: H01L25/0753 ,  H01L33/405 ,  H01L33/46 ,  H01L33/60 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48464 ,  H01L2924/01322 ,  H05K1/111 ,  H05K2201/0391 ,  H05K2201/10106 ,  H05K2201/2054 ,  Y02P70/611 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A light emitting device includes a number of light emitting chips, a substrate to support the light emitting chips, a patterned first conductive layer over the substrate to facilitate radiation and reflection of light from the light emitting chips, and a patterned second conductive layer on the patterned first conductive layer, wherein the light emitting chips are located on the patterned second conductive layer.

Abstract translation: 发光器件包括多个发光芯片，用于支撑发光芯片的基板，在该基板上方的图形化的第一导电层，以便于来自发光芯片的光的辐射和反射;以及图案化的第二导电层， 图案化的第一导电层，其中发光芯片位于图案化的第二导电层上。

公开(公告)号：US20110199739A1

公开(公告)日：2011-08-18

申请号：US12873944

申请日：2010-09-01

Applicant: Nobuyuki Naganuma ,  Michimasa Takahashi ,  Masakazu Aoyama

Inventor： Nobuyuki Naganuma ,  Michimasa Takahashi ,  Masakazu Aoyama

IPC: H05K1/00 ,  H05K3/00

CPC classification number: H05K3/4691 ,  H05K2201/0391 ,  H05K2201/09127 ,  H05K2201/09854 ,  H05K2203/308 ,  Y10T29/49124

Abstract: A flex-rigid wiring board including an insulative substrate having a wiring layer which is formed on the insulative substrate and includes a conductor, a flexible wiring board positioned beside the insulative substrate and having a wiring layer, the wiring layer of the flexible wiring board including a conductor and being contained inside the flexible wiring board, and a first insulation layer positioned on the insulative substrate and the flexible wiring board such that a portion of the flexible wiring board is left exposed from the first insulation layer. The first insulation layer has a wiring layer which is formed on the first insulation layer and includes a conductor. The wiring layer of the first insulation layer has a thickness which is formed thicker than a thickness of the wiring layer of the flexible wiring board and a thickness of the wiring layer of the insulative substrate.

Abstract translation: 一种柔性刚性布线板，包括具有布线层的绝缘基板，所述布线层形成在所述绝缘基板上并且包括导体，柔性布线板位于所述绝缘基板的旁边并具有布线层，所述柔性布线板的布线层包括 导体，并且被容纳在柔性布线板内部;以及第一绝缘层，其位于绝缘基板和柔性布线板上，使得柔性布线板的一部分从第一绝缘层露出。 第一绝缘层具有形成在第一绝缘层上并包括导体的布线层。 第一绝缘层的布线层的厚度比柔性布线基板的布线层的厚度和绝缘基板的布线层的厚度厚。