公开(公告)号：US09468100B2

公开(公告)日：2016-10-11

申请号：US14325574

申请日：2014-07-08

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yoshihito Otsubo

IPC: H05K1/11 ,  H01L23/498 ,  H05K1/02 ,  H05K3/46

CPC classification number: H05K1/115 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/15174 ,  H05K1/0271 ,  H05K1/0298 ,  H05K3/4629 ,  H05K2201/09227 ,  H05K2201/09272 ,  H05K2201/09709 ,  H01L2924/00012

Abstract: A multilayer wiring substrate is provided which is less apt to cause the warping and the degradation of the surface flatness, and which is able to effectively suppress the occurrence of cracks. A multilayer wiring substrate 1 includes a substrate body 2 in which a plurality of wirings 5a are disposed to extend from a first principal surface 2a toward a second principal surface 2b. The wiring 5a or 5b includes via conductors 6a and 8a disposed respectively in at least two insulator layers in which the wiring is disposed, a wiring conductor 7a connecting the via conductor 6a, which is disposed in one 2c of the insulator layers adjacent to each other in a stacking direction of the insulator layers, and the via conductor 8a disposed in the other insulator layer 2d, the wiring conductor 7a having a nonlinear shape.

Abstract translation: 提供了不易引起翘曲和表面平坦度劣化的多层布线基板，并且能够有效地抑制裂纹的发生。 多层布线基板1包括：基板主体2，其中多个布线5a布置成从第一主表面2a朝向第二主表面2b延伸。 布线5a或5b包括通孔导体6a和8a，它们分别布置在其中布置布线的至少两个绝缘体层中;连接通孔导体6a的布线导体7a，布线导体7a布置在彼此相邻的绝缘体层的一个2c中 在绝缘体层的层叠方向和布置在另一个绝缘体层2d中的通路导体8a，布线导体7a具有非线性形状。

公开(公告)号：US20160270228A1

公开(公告)日：2016-09-15

申请号：US14695936

申请日：2015-04-24

Applicant: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD ,  HON HAI PRECISION INDUSTRY CO., LTD.

Inventor： HSIEN-PEI LUNG ,  WU-ZHE YU

IPC: H05K1/11 ,  H05K5/00 ,  H05K1/02

CPC classification number: H05K1/115 ,  H05K1/0215 ,  H05K1/116 ,  H05K5/0026 ,  H05K2201/09272 ,  H05K2201/09572

Abstract: A circuit board includes a substrate defining a plurality of ground attaching holes and a plurality of first through-holes. The substrate includes a first surface and a side edge. Wherein, a plurality of parallel and spaced first conductive paths is formed on the first surface around each ground attaching hole. A first arcuate conductive portion is formed at each end of each first conductive path. An angle between each first conductive path and the side edge is 45° or 135°. The first through-holes respectively extend through the first arcuate conductive portions and electrically couple with the first conductive paths.

Abstract translation: 电路板包括限定多个接地安装孔和多个第一通孔的基板。 基板包括第一表面和侧边缘。 其中，在每个接地连接孔周围的第一表面上形成多个平行和间隔的第一导电路径。 第一弧形导电部分形成在每个第一导电路径的每一端。 每个第一导电路径和侧边缘之间的角度为45°或135°。 第一通孔分别延伸穿过第一弧形导电部分并与第一导电路径电耦合。

公开(公告)号：US20160165728A1

公开(公告)日：2016-06-09

申请号：US14565360

申请日：2014-12-09

Applicant: Scott Francis Fullam ,  Patrick Timothy Codd ,  Agustya Ruchir Mehta

Inventor： Scott Francis Fullam ,  Patrick Timothy Codd ,  Agustya Ruchir Mehta

IPC: H05K1/18 ,  H05K1/02

CPC classification number: H05K1/0253 ,  H05K1/0224 ,  H05K1/0243 ,  H05K2201/0391 ,  H05K2201/09272 ,  H05K2201/09681 ,  H05K2201/09727 ,  H05K2201/09736

Abstract: Embodiments are disclosed for a printed circuit board. An example printed circuit board includes a ground plane comprising a pattern of an electrically conductive material. The example printed circuit board further includes a circuit trace disposed adjacent to the ground plane, where one or more characteristics of one of more of the pattern of the electrically conductive material in the ground plane and the circuit trace vary based upon a directional change of the circuit trace.

Abstract translation: 公开了印刷电路板的实施例。 示例性印刷电路板包括包括导电材料图案的接地平面。 示例性印刷电路板还包括邻近接地平面布置的电路迹线，其中接地平面中的导电材料的图案中的一个或多个特征中的一个或多个特性和电路迹线基于 电路痕迹。

公开(公告)号：US20150173195A1

公开(公告)日：2015-06-18

申请号：US14558614

申请日：2014-12-02

Applicant: CANON KABUSHIKI KAISHA

Inventor： Takashi Aoki ,  Yasuhiro Sawada

IPC: H05K1/18 ,  H05K1/11

CPC classification number: H05K1/111 ,  H05K1/0243 ,  H05K3/3442 ,  H05K2201/09272 ,  H05K2201/09427 ,  H05K2201/09727 ,  H05K2201/0979 ,  H05K2201/10015 ,  H05K2201/10636 ,  H05K2201/10651 ,  Y02P70/611

Abstract: An electronic component mounting structure includes a first land, a second land making a pair with the first land, an electronic component having a chip shape and including a first electrode connected to the first land and a second electrode connected to the second land, a first wiring pattern connected to the first land, and a second wiring pattern connected to the second land and including a first partial pattern overlapping a portion of a body of the electronic component in planar view, the portion being not covered with the pair of electrodes, a second partial pattern formed integral with the first partial pattern and overlapping the first electrode of the electronic component in planar view, and a third partial pattern formed integral with the second partial pattern and parallel to the first wiring pattern.

Abstract translation: 一种电子部件安装结构，包括第一焊盘，与第一焊盘成对的第二焊盘，具有芯片形状的电子部件，并且包括连接到第一焊盘的第一电极和连接到第二焊盘的第二电极，第一焊盘 连接到第一焊盘的布线图案和连接到第二焊盘的第二布线图案，并且包括在平面图中与电子部件的主体的一部分重叠的第一部分图案，该部分未被该对电极覆盖， 第二部分图案与第一部分图案整体形成并且在平面图中与电子部件的第一电极重叠，以及与第二部分图案一体形成并平行于第一布线图案的第三部分图案。

公开(公告)号：US20150092359A1

公开(公告)日：2015-04-02

申请号：US14447044

申请日：2014-07-30

Applicant: LG INNOTEK CO., LTD.

Inventor： In Tae Kim ,  Hyun Soo Kim ,  Jun Sik Shin ,  Joon Hyuk Yang ,  Jae Hong Lee ,  Chan Kyu Koo

IPC: H05K1/02 ,  G06F1/16 ,  G06F3/041

CPC classification number: H05K1/0296 ,  G06F1/1643 ,  G06F1/1652 ,  G06F3/0412 ,  G06F3/044 ,  G06F2203/04112 ,  H05K2201/09245 ,  H05K2201/09272

Abstract: Disclosed are a touch window with an improved visibility and a touch device with the same. The touch window includes a substrate; a first sensing electrode aligned on the substrate as a first conductive pattern; and a second sensing electrode aligned on the substrate as a second conductive pattern, wherein the first conductive pattern and the second conductive pattern have mutually different directionalities.

Abstract translation: 公开了具有改进的可见性的触摸窗口和具有其的触摸设备。 触摸窗包括基板; 第一感测电极，其在所述基板上对准，作为第一导电图案; 以及作为第二导电图案在所述基板上对准的第二感测电极，其中所述第一导电图案和所述第二导电图案具有相互不同的方向。

公开(公告)号：US08941012B2

公开(公告)日：2015-01-27

申请号：US13792243

申请日：2013-03-11

Applicant: Novatek Microelectronics Corp.

Inventor： Yu-Chang Pai

IPC: H05K1/09 ,  H05K1/02

CPC classification number: H05K1/0228 ,  H05K1/0224 ,  H05K1/0245 ,  H05K1/0253 ,  H05K1/0393 ,  H05K1/09 ,  H05K2201/09272 ,  H05K2201/09681

Abstract: A ground line structure adapted to a flexible circuit board is provided. The ground line structure includes a plurality of ground line structure units located on the flexible circuit board to form a meshed pattern. The ground line structure units include a plurality of ground line edge segments, a ground line middle segment and a plurality of ground line connecting segments. The ground line edge segments define an edge shape of each ground line structure unit. The edge shape of each ground line structure unit is a hexagon. The ground line connecting segments are configured to connect the ground line middle segment and the ground line edge segments. The ground line edge segments, the ground line middle segment and the ground line connecting segments form a plurality of pentagonal electrode structures within the hexagonal ground line structure unit. A flexible circuit board including the ground line structure is also provided.

Abstract translation: 提供了适用于柔性电路板的接地线结构。 地线结构包括位于柔性电路板上的多个接地线结构单元，以形成网格图案。 接地线结构单元包括多个接地线边缘段，地线中间段和多个接地线连接段。 地线边缘段限定每个接地线结构单元的边缘形状。 每个地线结构单元的边缘形状是六边形。 接地线连接段配置为连接接地线中间段和接地线边缘段。 接地线边缘段，地线中间段和接地线连接段在六边形接地线结构单元内形成多个五边形电极结构。 还提供了包括接地线结构的柔性电路板。

公开(公告)号：US20150013901A1

公开(公告)日：2015-01-15

申请号：US14327916

申请日：2014-07-10

Applicant: HSIO TECHNOLOGIES, LLC

Inventor： JAMES RATHBURN

IPC: H05K3/46 ,  H05K3/12 ,  H01L21/768 ,  H05K3/18

CPC classification number: H01L21/76877 ,  B33Y80/00 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H05K1/0393 ,  H05K1/16 ,  H05K3/0005 ,  H05K3/4069 ,  H05K3/421 ,  H05K3/429 ,  H05K3/465 ,  H05K3/4658 ,  H05K2201/09272 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/098 ,  H05K2203/013 ,  H05K2203/1476 ,  H01L2924/00014

Abstract: A system and method for “pixelating” a three-dimensional circuit structure into a three-dimensional matrix of cubes that are located with respect to a coordinate system. The design step is typically performed on a conventional computer using computer aided design software that pixelates the proposed circuit structure into an array of uniformly sized cube. The fabrication process involves adding and subtracting bulk materials from the individual cubic positions within the pixelated representation of the circuit structure. Various existing and new techniques can be used to add or subtract bulk materials as the cubic positions within the matrix to construct the circuit structure.

Abstract translation: 将三维电路结构“像素化”为相对于坐标系定位的三维矩阵的三维矩阵的系统和方法。 设计步骤通常在使用计算机辅助设计软件的常规计算机上执行，将所提出的电路结构像素化为均匀尺寸的立方体的阵列。 制造过程包括在电路结构的像素化表示内从各个立方体位置添加和减去大量材料。 可以使用各种现有技术和新技术将体积材料作为立方体位置加入或减去以构成电路结构。

公开(公告)号：US20140209359A1

公开(公告)日：2014-07-31

申请号：US13751464

申请日：2013-01-28

Applicant: JOHN ANDREW LEBENS ,  David Paul Trauernicht ,  Yongcai Wang ,  Ronald Steven Cok

Inventor： JOHN ANDREW LEBENS ,  David Paul Trauernicht ,  Yongcai Wang ,  Ronald Steven Cok

IPC: H05K1/02

CPC classification number: H05K1/0296 ,  G06F3/044 ,  H05K1/02 ,  H05K1/0289 ,  H05K3/1258 ,  H05K2201/0108 ,  H05K2201/0376 ,  H05K2201/09227 ,  H05K2201/09272 ,  H05K2201/09681 ,  H05K2201/09727 ,  Y10T428/26

Abstract: A conductive micro-wire structure includes a substrate. A plurality of spaced-apart electrically connected micro-wires is formed on or in the substrate forming the conductive micro-wire structure. The conductive micro-wire structure has a transparency of less than 75% and greater than 0%.

Abstract translation: 导电微线结构包括衬底。 多个间隔开的电连接的微线形成在形成导电微线结构的衬底上或衬底中。 导电微线结构具有小于75％且大于0％的透明度。

公开(公告)号：US20140054795A1

公开(公告)日：2014-02-27

申请号：US13591719

申请日：2012-08-22

Applicant: Matthew David Romig ,  Lance Cole Wright ,  Leslie Edward Stark ,  Frank Stepniak ,  Sreenivasan K. Koduri

Inventor： Matthew David Romig ,  Lance Cole Wright ,  Leslie Edward Stark ,  Frank Stepniak ,  Sreenivasan K. Koduri

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H01L23/00 ,  B41M3/06 ,  H01L23/48 ,  H01L24/24 ,  H01L24/25 ,  H01L24/76 ,  H01L24/80 ,  H01L24/82 ,  H01L25/0657 ,  H01L2224/24145 ,  H01L2224/24227 ,  H01L2224/321 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/76155 ,  H01L2224/82102 ,  H05K1/092 ,  H05K1/181 ,  H05K3/125 ,  H05K3/32 ,  H05K2201/09272 ,  H05K2201/10151 ,  H05K2201/10454 ,  Y02P70/611

Abstract: One method of making an electronic assembly includes mounting one electrical substrate on another electrical substrate with a face surface on the one substrate oriented transversely of a face surface of the other substrate. The method also includes inkjet printing on the face surfaces a conductive trace that connects an electrical contact on the one substrate with an electrical connector on the other substrate. An electronic assembly may include a first substrate having a generally flat surface with a first plurality of electrical contacts thereon; a second substrate having a generally flat surface with a second plurality of electrical contacts thereon, the surface of the second substrate extending transversely of the surface of said first substrate; and at least one continuous conductive ink trace electrically connecting at least one of the first plurality of electrical contacts with at least one of the second plurality of electrical contacts.

Abstract translation: 制造电子组件的一种方法包括将一个电气基板安装在另一个电气基板上，其中一个基板上的面表面横向于另一个基板的表面。 该方法还包括在表面上喷墨印刷导电迹线，导电迹线将一个基底上的电接触与另一基底上的电连接器连接。 电子组件可以包括具有大致平坦表面的第一基板，其上具有第一多个电触点; 第二基板，其具有大致平坦的表面，其上具有第二多个电触点，所述第二基板的表面横向于所述第一基板的表面延伸; 以及至少一个连续的导电油墨迹线将所述第一多个电触点中的至少一个与所述第二多个电触点中的至少一个电连接。

公开(公告)号：US20140049929A1

公开(公告)日：2014-02-20

申请号：US13960469

申请日：2013-08-06

Applicant: Canon Kabushiki Kaisha

Inventor： Hiroyuki Yamaguchi

IPC: H05K1/02

CPC classification number: H05K1/0216 ,  H05K1/0231 ,  H05K1/0233 ,  H05K1/0245 ,  H05K2201/0792 ,  H05K2201/09272 ,  H05K2201/09418 ,  H05K2201/10522 ,  H05K2201/10636 ,  Y02P70/611

Abstract: A filter circuit 103 includes capacitor elements 121 and 122. The capacitor element 121 returns a common mode current included in a signal output from, a signal output terminal 111 of a semiconductor element 102, to a ground terminal 113 of the semiconductor element 102. The capacitor element 122 returns a common mode current included in a signal output from a signal output terminal 112 of the semiconductor element 102, to the ground terminal 113 of the Semiconductor element 102. The capacitor elements 121 and 122 are arranged such that the mutual inductance between a parasitic inductance of the capacitor element 121 and a parasitic inductance of the capacitor element 122 for the common mode currents is a negative value. Accordingly, the effective inductances of the first and second capacitor elements for the common mode currents are reduced, which suppresses radiation noise.

Abstract translation: 滤波器电路103包括电容器元件121和122.电容器元件121将包括在从半导体元件102的信号输出端子111输出的信号中的共模电流返回到半导体元件102的接地端子113。 电容器元件122将包括在从半导体元件102的信号输出端子112输出的信号中的共模电流返回到半导体元件102的接地端子113.电容器元件121和122被布置成使得 电容器元件121的寄生电感和用于共模电流的电容器元件122的寄生电感为负值。 因此，减小了用于共模电流的第一和第二电容器元件的有效电感，这抑制了辐射噪声。