Abstract:
A method of manufacturing a package structure is provided, including forming a first wiring layer on a carrier board, forming up plurality of first conductors on the first wiring layer, forming a first insulating layer that encapsulates the first wiring layer and the first conductors, forming a second wiring layer on the first insulating layer, forming a plurality of second conductors on the second wiring layer, forming a second insulating layer that encapsulates the second wiring layer and the second conductors, and forming at least an opening on the second insulating layer for at least one electronic component to be disposed therein. Since the first and second insulating layers are formed before the opening, there is no need of stacking or laminating a substrate that already has an opening, and the electronic component will not be laminated and make a displacement. Therefore, the package structure thus manufactured has a high yield rate. The present invention further provides the package structure.
Abstract:
A filter circuit component includes desired frequency characteristics without being influenced by a parasitic inductance and a parasitic capacitance, and since the ground terminal of the filter circuit component connected to the mounting electrode of the high-frequency component is connected to the ground electrode of the high-frequency component through the via conductors of the high-frequency component at the shortest distance, the packing density of the filter circuit component is significantly increased and the occurrence of an unnecessary parasitic inductance and an unnecessary parasitic capacitance is prevented. The filter circuit component is mounted on the high-frequency component to obtain the desired frequency characteristics without the influence of a parasitic inductance and a parasitic capacitance. Since the component is located in a space surrounded by the inner peripheral surface of the supporting frame body, the packing density of components mounted on the high-frequency component is increased.
Abstract:
The wired circuit board includes a conductive layer having a terminal; a gold plated layer provided on the surface of the terminal; and a solder layer provided on the surface of the gold plated layer and provided so that the terminal and the electronic component can be electrically connected. The solder layer is made of a solder composition containing Sn, Bi, Cu and/or Ni, and the thickness Tsolder of the solder layer relative to the thickness TAu of the gold plated layer is 16 or more.
Abstract:
An apparatus having reduced phononic coupling between a graphene monolayer and a substrate is provided. The apparatus includes an aerogel substrate and a monolayer of graphene coupled to the aerogel substrate.
Abstract:
To prevent decrease of the bonding strength of an electronic component and a multilayer substrate, an electronic component-embedded module may include an electronic component having a plurality of pads and a multilayer substrate which includes a plurality of resin layers and a cavity for containing the electronic component. The multilayer substrate may include a first resin layer having a plurality of first pattern conductors and a space, and a second resin layer having a second pattern conductor and a plurality of third pattern conductors. The plurality of third pattern conductors may be in conduction with either of the first pattern conductors or the pads, with the second resin layer being placed over the first resin layer. The second pattern conductor may be arranged around a first pad with a gap, and the second resin layer is present between the second pattern conductor and at least one of the first pads.
Abstract:
An electronic part embedded substrate is disclosed. The electronic part embedded substrate includes a first substrate, a second substrate, an electronic part, an electrically connecting member, and a sealing member. A method of producing an electronic part embedded substrate is also disclosed. The method includes mounting an electronic part onto a first substrate, laminating a second substrate on the first substrate through an electrically connecting member; and filling a space between the first substrate and the second substrate with a sealing member to seal the electronic part.
Abstract:
Systems and methods for a feeding structure for an antenna array are provided. In at least one embodiment, the feeding structure for an antenna array comprises one or more circuit boards with one or more circuits formed thereon, one or more conductive layers wherein the one or more circuit boards are mounted to the one or more conductive layers, and one or more connectors coupled to the one or more circuits through an opening in the one or more conductive layers. Furthermore, the one or more conductive layers are separated by a dielectric from the one or more circuits and the one or more conductive layers contact the one or more circuit boards such that the one or more circuits are isolated from the one or more conductive layers.
Abstract:
A substrate board includes an electrical connection network on a face thereof. An integrated-circuit chip is mounted to the face of the substrate board in electrical contact with the electrical connection network. A local reinforcing or balancing layer made of a non-metallic material is mounted to the face of the substrate board in at least one local zone free of the face which is free of metal portions of the electrical connection network.
Abstract:
An apparatus having reduced phononic coupling between a graphene monolayer and a substrate is provided. The apparatus includes an aerogel substrate and a monolayer of graphene coupled to the aerogel substrate.
Abstract:
A method of producing a chip embedded substrate is disclosed. This method comprises a first step of mounting a semiconductor chip on a first substrate on which a first wiring is formed; and a second step of joining the first substrate with a second substrate on which a second wiring is formed. In the second step, the semiconductor chip is encapsulated between the first substrate and the second substrate and electrical connection is made between the first wiring and the second wiring so as to form multilayered wirings connected to the semiconductor chip.