公开(公告)号：US06595784B2

公开(公告)日：2003-07-22

申请号：US09855308

申请日：2001-05-15

Applicant: William Louis Brodsky ,  David Vincent Caletka

Inventor： William Louis Brodsky ,  David Vincent Caletka

IPC: H01R1200

CPC classification number: H05K1/036 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K1/0271 ,  H05K1/113 ,  H05K1/114 ,  H05K1/141 ,  H05K3/42 ,  H05K3/4644 ,  H05K2201/0133 ,  H05K2201/0154 ,  H05K2201/09063 ,  H05K2201/10378 ,  H01L2924/00

Abstract: An interposer member having strategically positioned apertures for electrically connecting an electronic device to a circuitized substrate. The member includes a homogeneous elastomer core having strategically positioned apertures. The apertures are positioned through the member approximately equidistant between adjacent plated through holes and/or conductive pads. Such positioning relieves stress from the plated through holes and/or conductive pads, and increases the contact compliancy of the member.

公开(公告)号：US06592783B2

公开(公告)日：2003-07-15

申请号：US09779480

申请日：2001-02-09

Applicant: Hiroyuki Kumakura ,  Satoshi Yamamoto

Inventor： Hiroyuki Kumakura ,  Satoshi Yamamoto

IPC: H01B120

CPC classification number: H01L24/83 ,  C08L63/00 ,  C09J7/10 ,  C09J9/02 ,  C09J2201/36 ,  C09J2201/602 ,  C09J2433/00 ,  C09J2463/00 ,  H01B1/22 ,  H01B3/18 ,  H01L24/29 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/83101 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01055 ,  H01L2924/0132 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/07811 ,  H01L2924/14 ,  H01R4/04 ,  H05K3/323 ,  H05K2201/0133 ,  H05K2201/0379 ,  H05K2201/10674 ,  H05K2203/1189 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49211 ,  Y10T156/1052 ,  Y10T428/254 ,  Y10T428/269 ,  Y10T428/2857 ,  Y10T428/2991 ,  Y10T428/2998 ,  H01L2924/00 ,  H01L2924/01028

Abstract: An anisotropic conductive adhesive film contains a first insulating adhesive layer, a second insulating adhesive layer whose modulus of elasticity after curing is less than the modulus of elasticity of the cured first insulating adhesive layer, and electrically conductive particles which are dispersed in at least either the first insulating adhesive layer or the second insulating adhesive layer.

Abstract translation: 各向异性导电粘合剂膜包含第一绝缘粘合剂层，固化后的弹性模量小于固化的第一绝缘粘合剂层的弹性模量的第二绝缘粘合剂层和分散在至少 第一绝缘粘合剂层或第二绝缘粘合剂层。

公开(公告)号：US20030115752A1

公开(公告)日：2003-06-26

申请号：US10365874

申请日：2003-02-13

Applicant: Micron Technology, Inc.

Inventor： James M. Wark ,  Salman Akram

IPC: H05K003/00 ,  H01R009/00

CPC classification number: H01R12/57 ,  G01R1/0408 ,  G01R1/0466 ,  H01L2924/0002 ,  H01R43/205 ,  H05K1/119 ,  H05K3/325 ,  H05K3/326 ,  H05K3/4007 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/09045 ,  H05K2201/09472 ,  H05K2201/10689 ,  Y10T29/49117 ,  Y10T29/49123 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49174 ,  Y10T29/49179 ,  Y10T29/49222 ,  Y10T29/49453 ,  H01L2924/00

Abstract: A method of making an interposer having an array of contact structures for making temporary electrical contact with the leads of a chip package. The contact structures may make contact with the leads substantially as close as desired to the body of the chip package. Moreover, the contact structures can be adapted for making contact with leads having a very fine pitch. In a first embodiment, the contact structures include raised members formed over a body of the interposer. A conductive layer is formed over each of the raised members to provide a contact surface for engaging the leads of the chip package. In another embodiment, the raised members are replaced with depressions formed into the interposer. A conductive layer is formed on an inside surface of each depression to provide a contact surface for engaging the leads of the chip package. Moreover, any combination of raised members and depressions may be used.

Abstract translation: 一种制造具有用于与芯片封装的引线暂时电接触的接触结构阵列的插入件的方法。 接触结构可以与引线基本上接近于芯片封装体的所需位置。 此外，接触结构可以适于与具有非常细的间距的引线接触。 在第一实施例中，接触结构包括形成在插入件的主体上的凸起部件。 在每个凸起构件上形成导电层，以提供用于接合芯片封装引线的接触表面。 在另一个实施例中，凸起构件被形成在插入件中的凹陷所代替。 在每个凹陷的内表面上形成导电层，以提供用于接合芯片封装的引线的接触表面。 此外，可以使用凸起构件和凹陷的任何组合。

公开(公告)号：US20030108764A1

公开(公告)日：2003-06-12

申请号：US10006989

申请日：2001-12-04

Inventor： John Thomas Neill ,  Luis Daniel Borges

IPC: B32B031/26

CPC classification number: B32B37/12 ,  B32B2311/00 ,  B32B2329/06 ,  B32B2398/10 ,  B32B2457/08 ,  C08J5/125 ,  C09J129/14 ,  H05K3/386 ,  H05K3/4626 ,  H05K3/4652 ,  H05K3/4655 ,  H05K2201/0133 ,  H05K2201/0358 ,  H05K2203/0759 ,  Y10T428/12514

Abstract: A method for enhancing the adhesion between a metal surface and a circuit board substrate comprises contacting the metal surface with adhesion promoting solution comprising poly(vinyl butyral) having a molecular weight of about 70,000 to about 200,000 and a carrier; allowing the carrier to evaporate and forming an adhesion promoting layer; contacting the adhesion promoting layer with a curable thermosetting circuit board substrate composition; and curing the thermosetting composition. Use of an adhesion promoting layer comprising poly(vinyl butyral) having a molecular weight of about 70,000 to about 200,000 causes a large increase in both the tensile bond strength between the metal surface and thermoset resin and the uniformity of the tensile bond strength.

Abstract translation: 一种用于增强金属表面和电路板基底之间的粘合力的方法包括使金属表面与包含分子量为约70,000至约200,000的聚（乙烯醇缩丁醛）和载体的粘合促进溶液接触; 允许载体蒸发并形成粘附促进层; 使粘合促进层与可固化的热固性电路板基底组合物接触; 并固化该热固性组合物。 使用包含分子量约70,000至约200,000的聚（乙烯醇缩丁醛）的粘合促进层使得金属表面和热固性树脂之间的拉伸粘合强度和拉伸粘合强度的均匀性都大大增加。

公开(公告)号：US20030102154A1

公开(公告)日：2003-06-05

申请号：US10342969

申请日：2003-01-15

Applicant: Tessera, Inc.

Inventor： Belgacem Haba

IPC: H05K001/11

CPC classification number: H01L21/568 ,  B29C70/62 ,  B29C70/882 ,  G02F1/1339 ,  H01L21/6835 ,  H01L23/49827 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/27438 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/29499 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/83851 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/12044 ,  H01L2924/14 ,  H05K3/323 ,  H05K3/368 ,  H05K3/4623 ,  H05K2201/0133 ,  H05K2201/0248 ,  H05K2201/083 ,  H05K2201/09536 ,  H05K2203/104 ,  H05K2203/105 ,  H01L2924/00

Abstract: A layer of an anisotropic material has a pair of substantially flat oppositely-directed major faces, a vertical direction extending between the faces and horizontal directions transverse to the vertical direction, the layer including a dielectric material and a plurality of conductive particles in the dielectric material. The particles are distributed non-uniformly in the horizontal directions so as to provide areas of high particle concentration interspersed with areas of low particle concentration.

Abstract translation: 各向异性材料层具有一对基本平坦的相反方向的主面，垂直方向在横向于垂直方向的面和水平方向之间延伸，所述层包括电介质材料和电介质材料中的多个导电颗粒 。 颗粒在水平方向上不均匀地分布，以提供散布有低颗粒浓度区域的高颗粒浓度的区域。

公开(公告)号：US20030101581A1

公开(公告)日：2003-06-05

申请号：US10338962

申请日：2003-01-08

Inventor： John S. Kresge ,  Voya R. Markovich

IPC: H05K003/36 ,  H05K003/42

CPC classification number: H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K1/114 ,  H05K3/4614 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4688 ,  H05K2201/0133 ,  H05K2201/10734 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49146 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: An electrical structure, and associated method of fabrication, for reducing thermally induced strain in a soldered interface, such as a solder ball or a solder column, between a chip carrier (or chip) and an electronic carrier such as a circuit card. The thermally induced strain may be caused during thermal cycling by a mismatch in coefficient of thermal expansion (CTE), and consequent differential rates in thermal expansion, between the chip carrier (or chip) and the electronic carrier. The thermally induced strain may also exist with a large chip carrier characterized by a large temperature difference during thermal transients between the electronic carrier and localized regions of the chip carrier, even in the absence of a CTE mismatch. The electrical structure of the present invention includes an interposing compliant layer of soft and spongy material between the chip carrier (or chip) and the electronic carrier. Thermal strains resulting from the differential rates of thermal expansion are diverted from the soldered interface into small motions of material within the compliant layer.

公开(公告)号：US06565977B2

公开(公告)日：2003-05-20

申请号：US09905918

申请日：2001-07-17

Applicant: Sang-Jun Bae ,  Sung-Il Oh

Inventor： Sang-Jun Bae ,  Sung-Il Oh

IPC: B32B2738

CPC classification number: H05K3/4661 ,  H05K2201/0133 ,  H05K2201/0195 ,  H05K2201/0209 ,  Y10S428/901 ,  Y10T428/24942 ,  Y10T428/31515 ,  Y10T428/31522

Abstract: In an insulating film having improved adhesive strength and a multilayer printed circuit board having the same, the insulating film made of an epoxy resin, a rubber and a filler, for use in an insulating layer of a multilayer printed circuit board, is composed of a first coating layer and a second coating layer. The first coating layer has a greater amount of rubber and filler and a smaller amount of epoxy resin than the second coating layer.

Abstract translation: 在具有改进的粘合强度的绝缘膜和具有该绝缘膜的多层印刷电路板中，由用于多层印刷电路板的绝缘层的环氧树脂，橡胶和填料制成的绝缘膜由 第一涂层和第二涂层。 第一涂层具有比第二涂层更大量的橡胶和填料和更少量的环氧树脂。

公开(公告)号：US20030091842A1

公开(公告)日：2003-05-15

申请号：US10252697

申请日：2002-09-24

Applicant: UBE INDUSTRIES, LTD.

Inventor： Tooru Murakami ,  Toyofumi Asano ,  Masahiro Imaizumi

IPC: B32B027/00

CPC classification number: H05K3/281 ,  H05K3/386 ,  H05K2201/0133 ,  H05K2201/0154 ,  H05K2201/0209 ,  Y10T428/1495 ,  Y10T428/2839 ,  Y10T428/287 ,  Y10T428/31511 ,  Y10T428/31515 ,  Y10T428/31522 ,  Y10T428/31547 ,  Y10T428/31721

Abstract: A cover-lay film comprising a heat-resistant film and an adhesive layer, wherein the adhesive layer is formed of an epoxy resin composition containing (a) an epoxy resin, (b) a curing agent, (c) a phenolic hydroxyl-containing polyamide-poly(butadiene-acrylonitrile) copolymer, and (d) an ion capturing agent and having a glass transition temperature of 80null C. or higher after cure, and the heat-resistant film mainly comprises a polyimide containing a 3,3null,4,4null-biphenyltetracarboxylic acid component and a p-phenylenediamine component and has a specific coefficient of linear thermal expansion and a specific tensile modulus in both machine and transverse directions.

Abstract translation: 1.一种覆盖膜，包括耐热膜和粘合剂层，其中所述粘合剂层由环氧树脂组合物形成，所述环氧树脂组合物包含（a）环氧树脂，（b）固化剂，（c）含酚羟基的 聚酰胺 - 聚（丁二烯 - 丙烯腈）共聚物，（d）离子捕获剂，固化后玻璃化转变温度为80℃以上，耐热膜主要包含含有3,3' 4,4'-联苯四羧酸组分和对苯二胺组分，并且在机器横向上具有特定的线性热膨胀系数和比拉伸模量。

公开(公告)号：US20030075270A1

公开(公告)日：2003-04-24

申请号：US10225395

申请日：2002-08-21

Inventor： Vincent R. Landi ,  Bryan C. McAlister ,  John T. Neill

IPC: C09J001/00

CPC classification number: H05K3/386 ,  H05K3/4626 ,  H05K3/4652 ,  H05K3/4655 ,  H05K2201/0133 ,  H05K2201/0355 ,  H05K2201/0358

Abstract: A method of forming a circuit material comprises disposing an adhesion promoting elastomer composition between a conductive copper foil and a thermosetting composition; and laminating the copper foil, adhesion promoting composition, and thermosetting composition to form the circuit material. The adhesion promoting layer may be uncured or partially cured before contacting with the curable thermosetting composition. Preferably the adhesion promoting layer has electrical characteristics such as dissipation factor, dielectric breakdown strength, water absorption, and dielectric constant that are similar to and/or compatible with the electrical characteristics of the thermosetting composition.

Abstract translation: 形成电路材料的方法包括在导电铜箔和热固性组合物之间设置粘合促进弹性体组合物; 并层压铜箔，粘合促进组合物和热固性组合物以形成电路材料。 在与可固化的热固性组合物接触之前，粘合促进层可以是未固化的或部分固化的。 优选地，粘附促进层具有类似于和/或与热固性组合物的电特性相容的电学特性，例如耗散因子，介电击穿强度，吸水率和介电常数。

公开(公告)号：US06535012B1

公开(公告)日：2003-03-18

申请号：US09568707

申请日：2000-05-11

Applicant: Alan G. Wood ,  Tim J. Corbett

Inventor： Alan G. Wood ,  Tim J. Corbett

IPC: G01R3128

CPC classification number: H01L24/80 ,  G01R1/0466 ,  G01R1/0483 ,  G01R1/0491 ,  G01R1/0735 ,  G01R3/00 ,  G01R31/2831 ,  G01R31/2855 ,  G01R31/2863 ,  G01R31/2867 ,  G01R31/2886 ,  G01R31/2889 ,  G01R31/2893 ,  H01L22/20 ,  H01L22/22 ,  H01L23/13 ,  H01L2224/16145 ,  H01L2225/06562 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15151 ,  H05K3/0058 ,  H05K3/0067 ,  H05K3/4007 ,  H05K3/423 ,  H05K2201/0133 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0307 ,  H05K2203/0723

Abstract: A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consists of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical test equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical test are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.

Abstract translation: 用于测试半导体晶片上的无引脚骰子的可重复使用的老化/测试夹具由两半组成。 测试夹具的前半部分是用于接收晶片的晶片腔板，第二半部分在晶片和电气测试设备之间建立电气连通。 刚性基板在其上具有与晶片电接触的导体。 在老化和电气测试完成之前，测试夹具不需要打开。 在老化应力和电气测试之后，可以将单个裸片或单独的封装裸片与封装裸片之间建立互为独立部件，阵列或簇的互连，或者作为单个部分或阵列。