公开(公告)号：US20080169568A1

公开(公告)日：2008-07-17

申请号：US11897200

申请日：2007-08-29

Applicant: Hideki Kotake ,  Kiyoshi Hyodo ,  Inetaro Kurosawa ,  Yukio Hashimoto ,  Toku Yoshino ,  Tomoo Iijima

Inventor： Hideki Kotake ,  Kiyoshi Hyodo ,  Inetaro Kurosawa ,  Yukio Hashimoto ,  Toku Yoshino ,  Tomoo Iijima

IPC: H01L21/768 ,  H01L23/538

CPC classification number: H05K3/4614 ,  H01L23/48 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/205 ,  H05K3/423 ,  H05K3/4617 ,  H05K3/462 ,  H05K3/4647 ,  H05K3/4652 ,  H05K3/4658 ,  H05K2201/0376 ,  H05K2203/0733 ,  H05K2203/1536 ,  H01L2924/00

Abstract: A multilayer interconnect element is provided which includes at least one dielectric element in which metal interconnect patterns are exposed at an outer surface thereof, the metal interconnect patterns having outer surfaces which are co-planar with an exposed outer surface of the dielectric element. In addition, multilayer interconnect elements are provided in which second interconnect elements which do not have co-planar interconnect patterns are integrated therewith as intermediate elements, and the resulting multilayer interconnect element has co-planar interconnect patterns.

Abstract translation: 提供了一种多层互连元件，其包括至少一个电介质元件，其中金属互连图案在其外表面处露出，金属互连图案具有与介电元件的暴露的外表面共平面的外表面。 此外，提供了多层互连元件，其中不具有共面互连图案的第二互连元件作为中间元件与其集成，并且所得到的多层互连元件具有共面互连图案。

公开(公告)号：US20080029890A1

公开(公告)日：2008-02-07

申请号：US11623562

申请日：2007-01-16

Applicant: David C. H. Cheng

Inventor： David C. H. Cheng

IPC: H01L23/52

CPC classification number: H01L23/552 ,  H01L21/4853 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/16 ,  H01L2224/24051 ,  H01L2224/24226 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3025 ,  H05K1/0218 ,  H05K1/187 ,  H05K3/20 ,  H05K3/4602 ,  H05K2201/0376 ,  H05K2201/09509 ,  H05K2201/10674 ,  H01L2224/0401

Abstract: An embedded chip package process is provided. First, a chip is connected to a first circuit layer on a carrier, and then a cover plate is pressed onto a dielectric material layer to make the chip embedded in the dielectric material layer so that a circuit board with an embedded chip is formed. The chip has at least a bump electrically connected to a bonding pad of the first circuit layer through a solder. With enhanced reliability and alignment in chip bonding, the flip-chip bonding process replaces the conventional method of Laser drilling and circuit fabrication.

Abstract translation: 提供嵌入式芯片封装程序。 首先，将芯片连接到载体上的第一电路层，然后将盖板压在电介质材料层上，使芯片嵌入电介质材料层，从而形成具有嵌入式芯片的电路板。 该芯片至少具有通过焊料电连接到第一电路层的焊盘的凸点。 通过提高芯片接合中的可靠性和对准性，倒装芯片接合工艺代替了传统的激光钻孔和电路制造方法。

公开(公告)号：US20070151756A1

公开(公告)日：2007-07-05

申请号：US11712943

申请日：2007-03-02

Applicant: Yoshihisa Yamashita ,  Hiroki Yabe ,  Takashi Ichiryu ,  Seiichi Nakatani ,  Satoru Tomekawa ,  Toshio Fujii ,  Seiji Karashima

Inventor： Yoshihisa Yamashita ,  Hiroki Yabe ,  Takashi Ichiryu ,  Seiichi Nakatani ,  Satoru Tomekawa ,  Toshio Fujii ,  Seiji Karashima

IPC: H05K1/16

CPC classification number: H05K3/4084 ,  G03G15/225 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H05K1/0393 ,  H05K3/102 ,  H05K3/1266 ,  H05K3/20 ,  H05K3/207 ,  H05K3/386 ,  H05K3/4652 ,  H05K2201/0376 ,  H05K2203/0143 ,  H05K2203/0195 ,  H05K2203/0517 ,  H05K2203/1189 ,  H05K2203/1572 ,  H01L2924/00

Abstract: A flexible substrate comprises a film, a first insulating resin layer on a front face of the film, a second insulating resin layer on a rear face of the film, a front-sided wiring pattern embedded in the first insulating resin layer, and a rear-sided wiring pattern embedded in the second insulating resin layer. A surface of the front-sided wiring pattern is flush with a surface of the first insulating resin layer, and a surface of the rear-sided wiring pattern is flush with a surface of the second insulating resin layer. A part of at least one of the front-sided wiring pattern and the rear-sided wiring pattern is dented toward a part of the other of the at least one of the front-sided wiring pattern and the rear-sided wiring pattern such that a portion of the front-sided wiring pattern and a portion of the rear-sided wiring pattern are jointed to each other to form a junction.

公开(公告)号：US07229293B2

公开(公告)日：2007-06-12

申请号：US11175448

申请日：2005-07-07

Applicant: Daisuke Sakurai ,  Kazuhiro Nishikawa ,  Norihito Tsukahara

Inventor： Daisuke Sakurai ,  Kazuhiro Nishikawa ,  Norihito Tsukahara

IPC: H01R12/00

CPC classification number: H05K3/361 ,  H01R12/52 ,  H01R43/0207 ,  H05K3/107 ,  H05K2201/0129 ,  H05K2201/0376 ,  H05K2201/10977 ,  H05K2203/0278 ,  H05K2203/065

Abstract: First circuit board 10 including first resin base material 12 which is softened by heating and has a fusing property, and a plurality of first conductor patterns 14 formed on a surface of first resin base material 12, and second circuit board 20 on which a plurality of second conductor patterns 24 are formed with the same pitch as that of first conductor patterns 14 are provided. In the configuration, first conductor patterns 14 and second conductor patterns 24 are brought into mechanical contact with each other to provide electrical conduction; first resin base material 12 covers first conductor patterns 14 and second conductor patterns 24 and is bonded to second resin base material 22 of second circuit board 20, thereby connecting first circuit board 10 and second circuit board 20 to each other.

Abstract translation: 第一电路板10包括通过加热软化并具有熔融特性的第一树脂基材12和形成在第一树脂基材12的表面上的多个第一导体图案14和第二电路板20， 形成与第一导体图案14相同的间距的第二导体图案24。 在该结构中，第一导体图案14和第二导体图案24彼此机械接触以提供导电; 第一树脂基材12覆盖第一导体图案14和第二导体图案24，并且被接合到第二电路板20的第二树脂基材22，从而将第一电路板10和第二电路板20彼此连接。

公开(公告)号：US20060270211A1

公开(公告)日：2006-11-30

申请号：US11419887

申请日：2006-05-23

Applicant: Junichi Nakamura ,  Yuji Kobayashi

Inventor： Junichi Nakamura ,  Yuji Kobayashi

IPC: H01L21/82 ,  H01L21/4763

CPC classification number: H05K1/115 ,  H01L21/4857 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81001 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H05K1/116 ,  H05K3/205 ,  H05K3/28 ,  H05K3/3473 ,  H05K3/4007 ,  H05K3/421 ,  H05K3/423 ,  H05K3/4644 ,  H05K2201/0376 ,  H05K2201/09481 ,  H05K2201/0949 ,  H05K2201/09509 ,  H05K2203/0338 ,  H05K2203/0361 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of fabricating a wiring board characterized in comprising a first step of forming a first solder resist layer on a support board and forming a first opening portion at the first solder resist layer, a second step of forming an electrode at the first opening portion, a third step of forming an insulating layer on the electrode and forming a wiring portion connected to the electrode at the insulating layer, a fourth step of forming a second solder resist layer on the wiring portion and forming a second opening portion at the second solder resist layer, and a fifth step of removing the support board.

Abstract translation: 一种制造布线板的方法，其特征在于包括在支撑板上形成第一阻焊层并在第一阻焊层形成第一开口部分的第一步骤，在第一开口部分形成电极的第二步骤， 在所述电极上形成绝缘层并形成与所述绝缘层上的所述电极连接的布线部分的第三步骤;在所述布线部分上形成第二阻焊层并在所述第二阻焊层形成第二开口部分的第四步骤; 层，以及除去支撑板的第五步骤。

公开(公告)号：US20060221586A1

公开(公告)日：2006-10-05

申请号：US11117511

申请日：2005-04-29

Applicant: Hsin-Chen Yang

Inventor： Hsin-Chen Yang

IPC: H05K1/18

CPC classification number: H01L23/49861 ,  H01L23/49548 ,  H01L2924/0002 ,  H05K1/111 ,  H05K3/06 ,  H05K3/3442 ,  H05K2201/0376 ,  H05K2201/09745 ,  H05K2201/09881 ,  H05K2201/10636 ,  H05K2203/0369 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00

Abstract: A packaging substrate includes an array of packaging units. Each packaging unit has a chip pad carrying a chip, a plurality of pins arranged around the chip pad and spaced from one another and the chip pad by an open space, an insulative member filling up the open space, passive components each connected between two pins, a bonding adhesive applied to the pins to which the passive components is connected to affix the connection between the passive components and the respective pins, and a plurality of overflow-preventive grooves respectively provided around the bonding adhesive at each of the pins to which the passive components are connected to prevent overflow of the bonding adhesive.

Abstract translation: 包装衬底包括一组包装单元。 每个包装单元具有载置芯片的芯片垫片，布置在芯片焊盘周围的多个引脚，彼此间隔开并且芯片焊盘由开放​​空间，填充开放空间的绝缘构件，各自连接在两个引脚之间的无源元件 施加到被连接无源部件的引脚上的粘合粘合剂以固定无源部件和相应引脚之间的连接，以及分别设置在每个引脚周围的粘合粘合剂周围的多个防溢流槽， 被动部件被连接以防止粘结粘合剂溢出。

公开(公告)号：US20060191715A1

公开(公告)日：2006-08-31

申请号：US11338771

申请日：2006-01-25

Applicant: Masayoshi Koyama ,  Yoshitake Hayashi ,  Kazuo Otani

Inventor： Masayoshi Koyama ,  Yoshitake Hayashi ,  Kazuo Otani

IPC: H05K1/11 ,  H05K3/40

CPC classification number: H05K3/4614 ,  H05K3/0035 ,  H05K3/20 ,  H05K3/4069 ,  H05K3/4652 ,  H05K3/4658 ,  H05K2201/0376 ,  H05K2201/0394 ,  H05K2201/0969 ,  H05K2203/0278 ,  H05K2203/0554 ,  H05K2203/1453 ,  Y10T29/49165

Abstract: Holes having the same diameter as via holes are formed in predetermined positions in advance when forming wiring patterns on releasable carriers. The carriers with the wiring patterns are bonded on an insulating material, and a laser beam is irradiated from the side of the carrier using the holes in the wiring pattern as a laser mask to form via holes in the insulating material. The via holes and the holes in the carrier are then filled with a conductive paste. With the holes in the carrier that are matched in position with the via holes, lands in the conductor layers are precisely positioned relative to the via holes. A multilayer circuit board thus produced has lower electrical connection resistance and excellent mountability with improved performances. Also a manufacturing method thereof is achieved.

Abstract translation: 当在可拆卸的载体上形成布线图案时，预先形成具有与通孔相同直径的孔。 具有布线图案的载体被接合在绝缘材料上，并且使用布线图案中的孔作为激光掩模从载体的侧面照射激光束，以在绝缘材料中形成通孔。 通孔和载体中的孔然后用导电浆料填充。 通过载体中与通孔的位置匹配的孔，导体层中的焊盘相对于通孔精确定位。 由此制造的多层电路板具有较低的电连接电阻和优异的安装性能，并具有改进的性能。 也可以实现其制造方法。

公开(公告)号：US20050252682A1

公开(公告)日：2005-11-17

申请号：US11125158

申请日：2005-05-10

Applicant: Tadanori Shimoto ,  Katsumi Kikuchi ,  Hideya Murai ,  Kazuhiro Baba ,  Hirokazu Honda ,  Keiichiro Kata

Inventor： Tadanori Shimoto ,  Katsumi Kikuchi ,  Hideya Murai ,  Kazuhiro Baba ,  Hirokazu Honda ,  Keiichiro Kata

IPC: H01L23/12 ,  H01L21/48 ,  H01L21/68 ,  H01L23/14 ,  H01L23/498 ,  H01L25/065 ,  H05K1/03 ,  H05K1/11 ,  H05K3/20 ,  H05K3/42

CPC classification number: H01L23/49816 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/145 ,  H01L23/49822 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0366 ,  H05K3/205 ,  H05K3/423 ,  H05K2201/0376 ,  H05K2201/068 ,  H05K2203/0733 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A wiring board has a base insulating film. The base insulating film has a thickness of 20 to 100 μm and is made of a heat-resistant resin which has a glass-transition temperature of 150° C. or higher and which contains reinforcing fibers made of glass or aramid. The base insulating film has the following physical properties (1) to (6) when an elastic modulus at a temperature of T° C. is given as DT (GPa) and a breaking strength at a temperature of T° C. is given as HT (MPa). (1) A coefficient of thermal expansion in the direction of thickness thereof is 90 ppm/K or less. (2) D23≧5 (3) D150≧2.5 (4) (D-65/D150)≦3.0 (5) H23≧140 (6) (H-65/H150)≦2.3

Abstract translation: 布线板具有基底绝缘膜。 基底绝缘膜的厚度为20〜100μm，由玻璃化转变温度为150℃以上的含有玻璃或芳族聚酰胺的增强纤维的耐热性树脂构成。 当在T℃的温度下的弹性模量为D T（GPa）时，基体绝缘膜具有以下物理性质（1）至（6））和在温度下的断裂强度 的T℃给出为H T（MPa）。 （1）其厚度方向的热膨胀系数为90ppm / K以下。 （2）D 23 = 5（3）D 150 > = 2.5（4）（D-65 / D 150 <= 3.0（5）H 23 = 140（6）（H-65 / H 150） 2.3

公开(公告)号：US20050140488A1

公开(公告)日：2005-06-30

申请号：US11017884

申请日：2004-12-22

Applicant: Koji Shimoyama ,  Nobuya Matsutani ,  Yuji Mido ,  Michio Ohba ,  Akihiko Ibata

Inventor： Koji Shimoyama ,  Nobuya Matsutani ,  Yuji Mido ,  Michio Ohba ,  Akihiko Ibata

IPC: H01F5/00 ,  H01F17/00 ,  H01F41/04 ,  H05K1/16 ,  H05K3/00 ,  H05K3/04 ,  H05K3/10 ,  H05K3/24 ,  H05K3/46

CPC classification number: H05K1/165 ,  H01F17/0006 ,  H05K3/0023 ,  H05K3/045 ,  H05K3/107 ,  H05K3/244 ,  H05K3/4614 ,  H05K3/465 ,  H05K2201/0376 ,  H05K2201/09036

Abstract: A coil electric conductor has an insulating substrate, a first conductive layer, and a second conductive layer. The first conductive layer is formed at a depression provided on a face of the insulating substrate. The second conductive layer is formed on the first conductive layer with the first conductive layer interposed between the second conductive layer and the insulating substrate. This construction realizes a coil electric conductor having a highly precisely uniformized cross-sectional shape.

Abstract translation: 线圈电导体具有绝缘基板，第一导电层和第二导电层。 第一导电层形成在设置在绝缘基板的表面上的凹陷处。 第二导电层形成在第一导电层上，第一导电层置于第二导电层和绝缘基板之间。 这种结构实现了具有高精度均匀横截面形状的线圈导电体。

公开(公告)号：US20040251537A1

公开(公告)日：2004-12-16

申请号：US10864870

申请日：2004-06-10

Inventor： Kyoung-sei Choi

IPC: H01L023/12

CPC classification number: H01L21/4846 ,  H01L21/3122 ,  H01L23/3107 ,  H01L23/4985 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H05K1/0393 ,  H05K3/045 ,  H05K3/06 ,  H05K3/107 ,  H05K3/1258 ,  H05K3/243 ,  H05K3/28 ,  H05K3/388 ,  H05K2201/0108 ,  H05K2201/0376 ,  H05K2201/09036 ,  H05K2203/0108 ,  Y10T29/49227 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A flexible substrate used in a semiconductor package, a method of manufacturing the same, and a semiconductor package including the flexible substrate. A circuit pattern forming region is formed in an insulating substrate with a dented shape and a circuit pattern formed of a metallic material is formed in the circuit pattern forming region.

Abstract translation: 用于半导体封装的柔性衬底，其制造方法以及包括柔性衬底的半导体封装。 电路图案形成区域形成在具有凹陷形状的绝缘基板中，并且在电路图案形成区域中形成由金属材料形成的电路图案。