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    Process of fabricating conductive column
    3.
    发明授权
    Process of fabricating conductive column 有权
    制造导电柱的工艺

    公开(公告)号：US07284323B2

    公开(公告)日：2007-10-23

    申请号：US10711863

    申请日：2004-10-11

    Applicant: David C. H. Cheng

    Inventor： David C. H. Cheng

    IPC: H01K3/10

    CPC classification number: H05K3/0047 ,  H05K3/0032 ,  H05K3/423 ,  H05K3/427 ,  H05K2201/09563 ,  H05K2201/09827 ,  H05K2203/1476 ,  H05K2203/1572 ,  Y10T29/49156 ,  Y10T29/49167

    Abstract: A fabrication process of a conductive column suitable for a fabrication of a circuit board. The circuit board comprises a dielectric layer. A first blind hole is formed in the dielectric layer from a second surface opposite to the first surface, wherein the blind end of the first blind hole connects to the blind end of the second blind hole. The first blind hole and the second blind hole constitute a through hole. The through hole is formed in an hourglass shape such that an inner diameter of the through hole near the first or the second surface is substantially larger than an inner diameter of the through hole near a middle portion of the through hole. A conductive material is filled in the though hole to form a conductive column.

    Abstract translation: 适用于制造电路板的导电柱的制造工艺。 电路板包括电介质层。 从与第一表面相对的第二表面在电介质层中形成第一盲孔，其中第一盲孔的盲端连接到第二盲孔的盲端。 第一个盲孔和第二个盲孔构成一个通孔。 通孔形成为沙漏形状，使得在第一或第二表面附近的通孔的内径基本上大于通孔的中间部分附近的通孔的内径。 导电材料填充在通孔中以形成导电柱。

    Hole metal-filling method
    7.
    发明授权
    Hole metal-filling method 失效
    孔金属填充法

    公开(公告)号：US06638858B2

    公开(公告)日：2003-10-28

    申请号：US10020700

    申请日：2001-10-30

    Applicant: David C. H. Cheng

    Inventor： David C. H. Cheng

    IPC: H01L2144

    CPC classification number: H05K3/4046 ,  H01L21/4853 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/0382 ,  H05K2201/10234

    Abstract: A hole metal-filling method, applied to hole filling and electroplating a printed circuit board which has been mechanical-drilled with holes. A plurality of holes is drilled in a substrate. The substrate is placed on a platform. A plurality of metal balls is disposed on a surface of the substrate. By vibrating the platform, a part of the metal balls roll into the holes, while the metal balls not rolling into the holes are removed. The substrate is then placed on a press down unit. The metal balls in the holes are pressed to level with surfaces of the substrate. The substrate is directly electroplated for forming a plating layer closely dovetail to the metal balls.

    Abstract translation: 孔金属填充方法，适用于已经机械钻孔的印刷电路板的孔填充和电镀。 在基板上钻出多个孔。 将基板放置在平台上。 多个金属球设置在基板的表面上。 通过振动平台，金属球的一部分滚动到孔中，而不会滚动到孔中的金属球被去除。 然后将基板放置在压下单元上。 孔中的金属球被压制以与基底的表面平齐。 将基板直接电镀以形成与金属球紧密接合的镀层。

    Method of forming IC package having downward-facing chip cavity
    8.
    发明授权
    Method of forming IC package having downward-facing chip cavity 有权
    形成具有向下的芯片腔的IC封装的方法

    公开(公告)号：US06506632B1

    公开(公告)日：2003-01-14

    申请号：US10078211

    申请日：2002-02-15

    Applicant: Jao-Chin Cheng ,  Chih-Peng Fan ,  David C. H. Cheng

    Inventor： Jao-Chin Cheng ,  Chih-Peng Fan ,  David C. H. Cheng

    IPC: H01L2144

    CPC classification number: H01L24/82 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/97 ,  H01L2224/45144 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2224/82 ,  H01L2924/00

    Abstract: A method of forming an integrated circuit package with a downward-facing chip cavity. A substrate comprising an insulating core layer and a conductive layer is provided. A through-hole is formed in the substrate and an adhesive tape is attached to the surface of the conductive layer. A silicon chip is attached to the exposed adhesive tape surface at the bottom of the first opening. The chip has an active surface and a back surface. The chip further includes a plurality of bonding pads on the active surface. The back surface of the chip is attached to the adhesive tape. A patterned dielectric layer is formed filling the first opening and covering a portion of the adhesive tape, the active surface, the bonding pad and the insulating core layer. The patterned dielectric layer has a plurality of openings that exposes the bonding pads and some through holes. A metallic layer is formed over the exposed surface of the openings and the upper surface of the patterned dielectric layer by electroplating. The adhesive tape is removed. The metallic layer and the conductive layer are patterned. A patterned solder resistant layer is formed over the metallic layer and the conductive layer. The patterned solder resistant layer has a plurality of openings that expose a portion of the conductive layer. A solder ball implant is conducted to form electrical connection between the solder balls and the conductive layer.

    Abstract translation: 一种形成具有朝下的芯片腔的集成电路封装的方法。 提供了包括绝缘芯层和导电层的衬底。 在基板中形成通孔，并且在导电层的表面上附着粘合带。 硅芯片附着在第一开口底部的暴露的胶带表面上。 芯片具有活性表面和背面。 所述芯片还包括在所述有源表面上的多个接合焊盘。 芯片的背面附着在胶带上。 形成图案化的介电层，填充第一开口并覆盖粘合带，活性表面，接合焊盘和绝缘芯层的一部分。 图案化电介质层具有暴露接合焊盘和一些通孔的多个开口。 通过电镀在开口的暴露表面和图案化电介质层的上表面上形成金属层。 去除胶带。 金属层和导电层被图案化。 在金属层和导电层之上形成图案化的阻焊层。 图案化的阻焊层具有暴露导电层的一部分的多个开口。 导电焊球植入物以形成焊球和导电层之间的电连接。

    PROCESS FOR FABRICATING CIRCUIT BOARD
    9.
    发明申请
    PROCESS FOR FABRICATING CIRCUIT BOARD 审中-公开
    制造电路板的工艺

    公开(公告)号：US20120124830A1

    公开(公告)日：2012-05-24

    申请号：US13362958

    申请日：2012-01-31

    Applicant: David C. H. Cheng ,  Shao-Chien Lee ,  Tzyy-Jang Tseng

    Inventor： David C. H. Cheng ,  Shao-Chien Lee ,  Tzyy-Jang Tseng

    IPC: H05K3/10

    CPC classification number: H05K3/4007 ,  H05K3/06 ,  H05K3/062 ,  H05K3/107 ,  H05K3/3452 ,  H05K2201/0341 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/099 ,  H05K2203/0384 ,  H05K2203/0542 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156

    Abstract: A process for fabricating a circuit board is provided. In the process, first, a circuit substrate including an insulation layer and at least a pad contacting the insulation layer is provided. Next, a barrier material layer is formed on the circuit substrate. The barrier material layer completely covers the insulation layer and the pad. Then, at least one conductive bump is formed on the barrier material layer. The conductive bump is opposite to the pad, and the material of the barrier material layer is different from the material of the conductive bump. Next, a portion of the barrier material layer is removed by using the conductive bump as a mask, so as to expose the surface of the insulation layer and to form a barrier connected between the conductive bump and the pad.

    Abstract translation: 提供一种制造电路板的工艺。 在该过程中，首先，提供包括绝缘层和至少与绝缘层接触的焊盘的电路基板。 接下来，在电路基板上形成阻挡材料层。 阻挡材料层完全覆盖绝缘层和垫。 然后，在阻挡材料层上形成至少一个导电凸块。 导电凸块与焊盘相对，并且阻挡材料层的材料与导电凸块的材料不同。 接下来，通过使用导电凸块作为掩模来去除阻挡材料层的一部分，以暴露绝缘层的表面并形成连接在导电凸块和焊盘之间的阻挡层。

    Embedded chip package process
    10.
    发明授权
    Embedded chip package process 有权
    嵌入式芯片封装过程

    公开(公告)号：US07888174B2

    公开(公告)日：2011-02-15

    申请号：US12234702

    申请日：2008-09-21

    Applicant: David C. H. Cheng

    Inventor： David C. H. Cheng

    IPC: H01L21/00 ,  H01L21/44 ,  H01L21/4763

    CPC classification number: H01L23/5389 ,  H01L23/5384 ,  H01L24/24 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/24051 ,  H01L2224/24226 ,  H01L2225/06541 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H05K1/187 ,  H05K3/20 ,  H05K3/4602 ,  H05K2201/0358 ,  H05K2201/10674

    Abstract: An embedded chip package process is disclosed. First, a first substrate having a first patterned circuit layer thereon is provided. Then, a first chip is disposed on the first patterned circuit layer and electrically connected to the first patterned circuit layer. A second substrate having a second patterned circuit layer thereon is provided. A second chip is disposed on the second patterned circuit layer and electrically connected to the second patterned circuit layer. Afterwards, a dielectric material layer is formed and covers the first chip and the first patterned circuit layer. Then, a compression process is performed to cover the second substrate over the dielectric material layer so that the second patterned circuit layer and the second chip on the second substrate are embedded into the dielectric material layer.

    Abstract translation: 公开了一种嵌入式芯片封装工艺。 首先，提供其上具有第一图案化电路层的第一基板。 然后，第一芯片设置在第一图案化电路层上并电连接到第一图案化电路层。 提供其上具有第二图案化电路层的第二基板。 第二芯片设置在第二图案化电路层上并电连接到第二图案化电路层。 之后，形成介电材料层并覆盖第一芯片和第一图案化电路层。 然后，执行压缩处理以覆盖电介质材料层上的第二衬底，使得第二图案化电路层和第二衬底上的第二芯片被嵌入电介质材料层中。

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