公开(公告)号：US09504153B2

公开(公告)日：2016-11-22

申请号：US14869596

申请日：2015-09-29

Applicant: LG DISPLAY CO., LTD.

Inventor： SoonJae Hwang ,  Ilgi Jeong

IPC: H01J1/62 ,  H05K1/11 ,  G02F1/1345 ,  H01L23/485 ,  H01L23/00 ,  H05B33/06 ,  H05K1/02 ,  H05K3/40 ,  G02F1/1362 ,  H01L23/538 ,  H01L21/768 ,  H01L27/12 ,  H05K3/36

CPC classification number: H05K1/111 ,  G02F1/13458 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/13629 ,  G02F2201/42 ,  H01L21/76804 ,  H01L21/76816 ,  H01L23/485 ,  H01L23/538 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L27/1244 ,  H01L27/3276 ,  H01L2224/04026 ,  H01L2224/05008 ,  H01L2224/05018 ,  H01L2224/05147 ,  H01L2224/0518 ,  H01L2224/05558 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/2929 ,  H01L2224/32145 ,  H01L2224/83203 ,  H01L2224/83365 ,  H01L2224/83851 ,  H05B33/06 ,  H05K1/0298 ,  H05K1/115 ,  H05K3/361 ,  H05K3/4007 ,  H05K2201/09227 ,  H05K2201/10128 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A display device includes a plurality of signal lines arranged in a display area of a substrate and a pad structure located at a non-active area and connected with the signal lines. The pad structure includes a plurality of metal layers and two or more insulating layers located between the metal layers and having one or more contact hole which makes two metal layers among the metal layers contacted with each other, and the contact holes respectively located in the insulating layers are not overlapped with each other.

Abstract translation: 显示装置包括布置在基板的显示区域中的多条信号线和位于非有效区域并与信号线连接的焊盘结构。 焊盘结构包括多个金属层和位于金属层之间的两个或更多个绝缘层，并且具有一个或多个使金属层中的两个金属层彼此接触的接触孔，并且分别位于绝缘层 层不彼此重叠。

公开(公告)号：US09480147B2

公开(公告)日：2016-10-25

申请号：US14483749

申请日：2014-09-11

Applicant: LG INNOTEK CO., LTD.

Inventor： Byeong Seob Kim ,  Ji Sung Ahn

IPC: H05K1/02 ,  G06F1/16 ,  G06F3/044 ,  H05K3/36

CPC classification number: H05K1/0259 ,  G06F1/1643 ,  G06F3/044 ,  G06F2203/04107 ,  H05K3/361 ,  H05K2201/09227 ,  H05K2201/09272 ,  H05K2201/09281 ,  H05K2201/09727

Abstract: A touch window includes a substrate, a sensing electrode on the substrate, a wire electrically connected with the sensing electrode, a ground wire adjacent to the wire, and a printed circuit board connected with the wire and the ground wire. An overlap length between the ground wire and the printed circuit board is longer than an overlap length between the wire and the printed circuit board. Alternatively or simultaneously, a line width of the ground wire is wider than an interval or gap between the wire parallel to the printed circuit.

Abstract translation: 触摸窗包括基板，基板上的感测电极，与感测电极电连接的导线，与导线相邻的接地线以及与导线和接地线连接的印刷电路板。 接地线和印刷电路板之间的重叠长度大于导线和印刷电路板之间的重叠长度。 或者或同时地，接地线的线宽比平行于印刷电路的线之间的间隔或间隙宽。

公开(公告)号：US09468100B2

公开(公告)日：2016-10-11

申请号：US14325574

申请日：2014-07-08

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yoshihito Otsubo

IPC: H05K1/11 ,  H01L23/498 ,  H05K1/02 ,  H05K3/46

CPC classification number: H05K1/115 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/15174 ,  H05K1/0271 ,  H05K1/0298 ,  H05K3/4629 ,  H05K2201/09227 ,  H05K2201/09272 ,  H05K2201/09709 ,  H01L2924/00012

Abstract: A multilayer wiring substrate is provided which is less apt to cause the warping and the degradation of the surface flatness, and which is able to effectively suppress the occurrence of cracks. A multilayer wiring substrate 1 includes a substrate body 2 in which a plurality of wirings 5a are disposed to extend from a first principal surface 2a toward a second principal surface 2b. The wiring 5a or 5b includes via conductors 6a and 8a disposed respectively in at least two insulator layers in which the wiring is disposed, a wiring conductor 7a connecting the via conductor 6a, which is disposed in one 2c of the insulator layers adjacent to each other in a stacking direction of the insulator layers, and the via conductor 8a disposed in the other insulator layer 2d, the wiring conductor 7a having a nonlinear shape.

Abstract translation: 提供了不易引起翘曲和表面平坦度劣化的多层布线基板，并且能够有效地抑制裂纹的发生。 多层布线基板1包括：基板主体2，其中多个布线5a布置成从第一主表面2a朝向第二主表面2b延伸。 布线5a或5b包括通孔导体6a和8a，它们分别布置在其中布置布线的至少两个绝缘体层中;连接通孔导体6a的布线导体7a，布线导体7a布置在彼此相邻的绝缘体层的一个2c中 在绝缘体层的层叠方向和布置在另一个绝缘体层2d中的通路导体8a，布线导体7a具有非线性形状。

公开(公告)号：US20160242298A1

公开(公告)日：2016-08-18

申请号：US15140779

申请日：2016-04-28

Applicant: Lattice Semiconductor Corporation

Inventor： Ban Pak Wong

IPC: H05K3/34 ,  H05K1/11 ,  G06F17/50 ,  H01L23/498 ,  H01L23/50

CPC classification number: H05K3/3436 ,  G06F17/5077 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/111 ,  H05K1/112 ,  H05K2201/09227 ,  H05K2201/10734 ,  Y02P70/613 ,  H01L2924/00

Abstract: In one embodiment, a ball grid array (BGA) of a packaged semiconductor device and a corresponding landing pad array of a printed circuit board each have a layout defined by an interconnection array having (i) an inner sub-array of locations having connectors arranged in rows and columns separated by a specified pitch and (ii) an outer rectangular ring of locations having connectors arranged in rows and columns separated by the specified pitch. The outer rectangular ring is separated from the inner sub-array by a depopulated rectangular ring having a width of at least twice the specified pitch, wherein the depopulated rectangular ring has no connectors. The outer rectangular ring has empty locations having no connectors. Some of those empty locations define depopulated sets that divide the outer rectangular ring into a number of different contiguous sets of locations having connectors that enable pin escape for connectors of the device's BGA.

公开(公告)号：US20160212854A1

公开(公告)日：2016-07-21

申请号：US14996298

申请日：2016-01-15

Applicant: IBIDEN CO., LTD.

Inventor： Nobuhisa KURODA ,  Hirofumi FUTAMURA

IPC: H05K1/18 ,  H05K1/02 ,  H05K3/30 ,  H05K3/00 ,  H05K3/46 ,  H05K1/03 ,  H05K1/11

CPC classification number: H05K1/0271 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5389 ,  H01L2224/16227 ,  H01L2224/81192 ,  H01L2924/15331 ,  H01L2924/18161 ,  H01L2924/3511 ,  H05K2201/09227 ,  H05K2201/10674

Abstract: A printed wiring board for mounting a semiconductor element includes an insulating substrate, a first conductor structure on first side of the substrate, and a second conductor structure on second side of the substrate. The substrate has a first area and a second area outside the first area such that when a semiconductor element is mounted on the first side, the first area is directly below the element, the first structure has a first area conductor structure in the first area and a second area conductor structure in the second area, and the first structure is formed such that first ratio is set greater than second ratio, where the first ratio is obtained by dividing volume of the first area structure by area of the first area structure, and the second ratio is obtained by dividing volume of the second area structure by area of the second area structure.

Abstract translation: 用于安装半导体元件的印刷线路板包括绝缘基板，在基板的第一侧上的第一导体结构和在基板的第二面上的第二导体结构。 基板在第一区域之外具有第一区域和第二区域，使得当半导体元件安装在第一侧上时，第一区域正好在元件下方，第一结构在第一区域中具有第一区域导体结构， 第二区域导体结构，并且第一结构形成为使得第一比例被设定为大于第二比例，其中通过将第一区域结构的体积除以第一区域结构的面积获得第一比例，以及 通过将第二区域结构的体积除以第二区域结构的面积来获得第二比例。

公开(公告)号：US20160183386A1

公开(公告)日：2016-06-23

申请号：US14617864

申请日：2015-02-09

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu SONG ,  Layal ROUHANA ,  Kyu-Pyung HWANG ,  Omar James BCHIR

IPC: H05K3/46 ,  H05K3/32 ,  H05K1/11 ,  H05K1/18 ,  H05K1/02

CPC classification number: H05K3/4644 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/0231 ,  H05K1/0234 ,  H05K1/0243 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/113 ,  H05K1/114 ,  H05K1/115 ,  H05K1/167 ,  H05K1/181 ,  H05K3/1258 ,  H05K3/321 ,  H05K3/3442 ,  H05K3/4697 ,  H05K2201/0792 ,  H05K2201/09227 ,  H05K2201/09281 ,  H05K2201/09954 ,  H05K2201/10015 ,  H05K2201/10636 ,  H05K2203/0545 ,  Y02P70/611

Abstract: Methods and apparatus for controlling an equivalent-series resistance (ESR) of a capacitor are provided. An exemplary apparatus includes a substrate having a land side, the capacitor mounted on the land side of the substrate and having both the ESR and terminals, a resistive pattern coupled to the terminals, and a plurality of vias coupled to the resistive pattern. The resistive pattern is configured to control the ESR. The resistive pattern can be formed of a resistive paste. The resistive pattern can be formed in a substantially semicircular shape having an arc ranging from substantially 45 degrees to substantially 135 degrees. The capacitor can be a surface mount device. The resistive pattern can be formed in a shape of a land-side capacitor mounting pad, a via, or both.

Abstract translation: 提供了用于控制电容器的等效串联电阻（ESR）的方法和装置。 示例性装置包括具有接地侧的基板，安装在基板的接地侧上并具有ESR和端子的电容器，耦合到端子的电阻图案以及耦合到电阻图案的多个通孔。 电阻模式被配置为控制ESR。 电阻图案可以由电阻浆料形成。 电阻图案可以形成为具有大致45度至基本上135度的弧度的大致半圆形状。 电容器可以是表面贴装器件。 电阻图案可以形成为陆侧电容器安装垫，通孔或两者的形状。

公开(公告)号：US09345124B2

公开(公告)日：2016-05-17

申请号：US14235811

申请日：2013-11-07

Applicant: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.

Inventor： Jianyong Fu

IPC: H05K7/00 ,  H05K1/02 ,  H01L23/48 ,  H01L23/552 ,  H05K1/09 ,  H05K1/11 ,  H05K1/18 ,  H01L23/50

CPC classification number: H05K1/0203 ,  H01L23/36 ,  H01L23/48 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/552 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/37001 ,  H05K1/0209 ,  H05K1/0231 ,  H05K1/092 ,  H05K1/115 ,  H05K1/18 ,  H05K2201/09227 ,  H05K2201/10015 ,  H05K2201/10522 ,  H05K2201/10674 ,  H05K2201/10969 ,  H01L2924/00

Abstract: The present invention provides a chip structure and a circuit structure, chip structure is disposed on a printed circuit board provided with an element layer and a copper grounding layer, and comprises: a chip body disposed on the element layer and having a plurality of power pins; a power line disposed on the element layer for supplying electric power to the chip body; a plurality of power input lines, each of which has a body disposed on the copper grounding layer and two ends disposed on the element layer and connected with the body through corresponding through holes of the printed circuit board; and a plurality of bypass capacitors having one end connected with the power pins of the chip body through the element layer and the other end of the bypass capacitors connected with the power line through the power input line. The present invention further provides a chip structure. The power line of the chip structure and the circuit structure of the present invention is disposed on the element layer, so that the heat dissipation effect of the copper grounding layer is better, and the yield of the chip and corresponding circuit structure is improved.

Abstract translation: 本发明提供了一种芯片结构和电路结构，芯片结构设置在具有元件层和铜接地层的印刷电路板上，包括：芯片体，设置在元件层上并具有多个电源引脚 ; 电源线，设置在所述元件层上，用于向所述芯片主体供电; 多个电源输入线，每个电源输入线具有布置在铜接地层上的主体和设置在元件层上的两端，并通过印刷电路板的相应通孔与主体相连; 以及多个旁路电容器，其一端通过元件层与芯片主体的电源引脚相连，旁路电容器的另一端通过电源输入线与电源线连接。 本发明还提供一种芯片结构。 芯片结构的电源线和本发明的电路结构设置在元件层上，使得铜接地层的散热效果更好，并且提高了芯片的产量和相应的电路结构。

公开(公告)号：US09282636B2

公开(公告)日：2016-03-08

申请号：US13893899

申请日：2013-05-14

Applicant: Johnson Electric S.A.

Inventor： Anthony Woodford ,  Calvin Linfield ,  Vincent Daniel Jean Salle ,  Kenneth Senior

IPC: H05K1/00 ,  G06K19/06 ,  H05K1/14 ,  H05K1/02 ,  H05K3/00 ,  G06K19/077 ,  H05K1/11

CPC classification number: H05K1/0296 ,  G06K19/07743 ,  H01L2224/97 ,  H05K1/0266 ,  H05K1/118 ,  H05K3/00 ,  H05K2201/09227 ,  Y10T156/1089

Abstract: A contact pad carrier strip includes a substrate having a lateral extent of or substantially of 35 mm or a multiple of or substantially of 35 mm, and at least three smart card contact pads formed along the lateral extent of the substrate. The contact pads are aligned widthwisely across the lateral extent of the substrate. Each smart card contact pad includes a plurality of contacts. A majority of contacts of the contact pads are oriented to extend widthwisely across the lateral extent of the carrier strip.

Abstract translation: 接触垫载体带包括具有35mm或基本上35mm的或基本上35mm的横向范围的基底，以及沿着基底的横向范围形成的至少三个智能卡接触垫。 接触垫沿横向横跨衬底的横向范围对准。 每个智能卡接触垫包括多个触点。 接触垫的大部分触点定向成横向延伸穿过载体条的横向范围。

公开(公告)号：US09258887B2

公开(公告)日：2016-02-09

申请号：US14016348

申请日：2013-09-03

Applicant: YAZAKI CORPORATION

Inventor： Yasushi Katayama

IPC: H05K1/00 ,  H05K1/02 ,  H05K3/00

CPC classification number: H05K1/0271 ,  H05K3/0005 ,  H05K2201/09227 ,  H05K2201/0969 ,  H05K2201/09781

Abstract: A printed circuit board is designed to meet the following requirements. A front-back copper foil residual rate difference a−b falls within a range of −10% to 10%, where the insulative board is divided into a plurality of divisions, in which front and back surface copper foil residual rates of each division are a % and b %, respectively. A difference (a−b)−(c−d) between front-back copper foil residual rate differences of adjacent divisions falls within a range of −10% to 10%, where the front and back surface copper foil residual rates of a division adjacent to the each division are c % and d %, respectively. There are not three or more consecutive divisions for which the difference between the front-back copper foil residual rate differences goes beyond a range of −5% to 5%.

Abstract translation: 印刷电路板设计符合以下要求。 前后铜箔残留率差a-b落在-10％〜10％的范围内，其中绝缘板被分成多个分区，其中各部分的前后铜箔残留率为 分别为％和b％。 相邻部分的前后铜箔残留率差异（a-b） - （c-d）在-10％至10％的范围内，其中前后铜箔残留率 分别为c％和d％。 前后铜箔剩余率差异之间的差异不超过-5％至5％的范围，不存在三个以上的连续分割。

公开(公告)号：US20160027724A1

公开(公告)日：2016-01-28

申请号：US14806803

申请日：2015-07-23

Applicant: KYOCERA Circuit Solutions, Inc.

Inventor： Takayuki ITO

IPC: H01L23/498 ,  H05K1/11 ,  H01L23/053

CPC classification number: H01L23/49822 ,  H01L23/04 ,  H01L23/10 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/16152 ,  H05K1/111 ,  H05K2201/09227 ,  H05K2201/10674 ,  H05K2201/10969 ,  H05K2201/10984 ,  Y02P70/611

Abstract: The wiring board of the present invention includes at least one insulating layer and at least one conductor layer being alternately laminated, a semiconductor element connection pad formed on an upper surface of the insulating layer at an uppermost layer of the insulating layers, a cap connection pattern arranged so as to surround a region where the semiconductor element connection pad is formed, and at least one strip-shaped pattern extending from the semiconductor element connection pad to a region outside an end portion on the region side of the cap connection pattern. The cap connection pattern is formed by a plurality of island-shaped patterns spaced apart from one another, and the strip-shaped pattern is formed between the adjacent island-shaped patterns on the upper surface of the insulating layer at the uppermost layer.

Abstract translation: 本发明的布线基板包括至少一个绝缘层和交替层叠的至少一个导体层，形成在绝缘层的最上层的绝缘层的上表面上的半导体元件连接焊盘，帽连接图案 被布置为围绕形成有半导体元件连接焊盘的区域，以及至少一个从半导体元件连接焊盘延伸到帽连接图案的区域侧的端部外侧的区域的条形图案。 帽连接图案由彼此间隔开的多个岛状图案形成，并且在最上层的绝缘层的上表面上的相邻岛状图案之间形成条形图案。