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    MOTHERBOARD AND MOTHERBOARD LAYOUT METHOD
    191.
    发明申请
    MOTHERBOARD AND MOTHERBOARD LAYOUT METHOD 有权
    主板和母板布局方法

    公开(公告)号：US20100277882A1

    公开(公告)日：2010-11-04

    申请号：US12503680

    申请日：2009-07-15

    Applicant: CHIA-NAN PAI ,  HAN-LONG CHEN ,  NING LI ,  SHOU-KUO HSU

    Inventor： CHIA-NAN PAI ,  HAN-LONG CHEN ,  NING LI ,  SHOU-KUO HSU

    IPC: H05K1/18 ,  H05K3/30

    CPC classification number: H05K1/0239 ,  H05K1/0245 ,  H05K1/0295 ,  H05K1/113 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09254 ,  H05K2201/10015 ,  H05K2201/10545 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/4913

    Abstract: A motherboard layout method includes positioning two electronic elements on a top layer of a motherboard, and positioning another two electronic elements on a bottom layer of the motherboard, connecting one end of a first electronic element on the top layer to the same end of a first electronic element on the bottom layer with a first via hole, and connecting the same end of a second electronic element on the top layer to the same end of a second electronic element on the bottom layer with a second via hole. The method further includes connecting the other ends of the two electronic elements on the top layer to a first part, and connecting the other ends of the two electronic elements on the bottom layer to a second part.

    Abstract translation: 主板布局方法包括将两个电子元件定位在主板的顶层上，并且将另外两个电子元件定位在母板的底层上，将顶层上的第一电子元件的一端连接到第一电子元件的同一端 电子元件在底层上具有第一通孔，并且通过第二通孔将顶层上的第二电子元件的同一端连接到底层上的第二电子元件的同一端。 该方法还包括将顶层上的两个电子元件的另一端连接到第一部分，并将底层上的两个电子元件的另一端连接到第二部分。

    Memory module and method having improved signal routing topology
    192.
    发明授权
    Memory module and method having improved signal routing topology 有权
    具有改进的信号路由拓扑的存储器模块和方法

    公开(公告)号：US07746095B2

    公开(公告)日：2010-06-29

    申请号：US12480589

    申请日：2009-06-08

    Applicant: George E. Pax ,  Roy E. Greeff

    Inventor： George E. Pax ,  Roy E. Greeff

    IPC: H03K19/003

    CPC classification number: G11C5/04 ,  G11C5/025 ,  G11C5/063 ,  G11C11/409 ,  H05K1/025 ,  H05K1/181 ,  H05K2201/09254 ,  Y02P70/611

    Abstract: A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends to either another transmission line or one of the memory devices. The branches are arranged in several layers of hierarchy, with the transmission lines in branches having the same hierarchy having the same length. Each transmission line preferably has a characteristic impedance that is half the characteristic impedance of any pair of downstream transmission lines to which it is coupled to provide impedance matching. A dedicated transmission line is used to couple an additional memory device, which may or may not be an error checking memory device, to the register.

    Abstract translation: 注册的存储器模块包括通过形成对称树形拓扑的多条传输线耦合到寄存器的多个存储器件。 树包括几个分支，每个分支包括仅在其端部耦合到另一个传输线或一个存储器件的两个传输线。 分支被布置成几层次，分支中的传输线具有相同长度的相同层级。 每个传输线优选地具有特性阻抗，其是与其耦合的任何一对下游传输线的特性阻抗的一半以提供阻抗匹配。 专用传输线用于将附加的存储器件（其可能是或可能不是错误检查存储器件）耦合到寄存器。

    LAYOUT CIRCUIT
    195.
    发明申请
    LAYOUT CIRCUIT 有权
    布局电路

    公开(公告)号：US20080257583A1

    公开(公告)日：2008-10-23

    申请号：US11853061

    申请日：2007-09-11

    Applicant: Ching-Chih Li

    Inventor： Ching-Chih Li

    IPC: H05K1/02

    CPC classification number: H05K1/112 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/06 ,  H01L2924/14 ,  H05K2201/09227 ,  H05K2201/09254 ,  H05K2201/10734 ,  H01L2924/00

    Abstract: The layout circuit comprises a first 3×2 grid array and a second 3×2 grid array. The first 3×2 grid array comprises first, second and third signal contact points and the first and second fixed potential contact points are coupled to a first fixed potential. The first and second fixed potential contact points are arranged diagonally into the first 2×2 array and the first and second signal contact points are also arranged diagonally into the first 2×2 array. The second 3×2 grid array comprises fourth, fifth and sixth signal contact points and the third and fourth fixed potential contact points are coupled to the first fixed potential. The third and fourth fixed potential contact points are arranged diagonally into the second 2×2 array and the fourth and fifth signal contact points are also arranged diagonally into the second 2×2 array.

    Abstract translation: 布局电路包括第一3×2网格阵列和第二3×2网格阵列。 第一3×2网格阵列包括第一，第二和第三信号接触点，并且第一和第二固定电位接触点耦合到第一固定电位。 第一和第二固定电位接触点被对角地布置到第一2x2阵列中，并且第一和第二信号接触点也被对角地布置到第一2x2阵列中。 第二3×2网格阵列包括第四，第五和第六信号接触点，并且第三和第四固定电位接触点耦合到第一固定电位。 第三和第四固定电位接触点被对角地布置到第二2x2阵列中，并且第四和第五信号接触点也被对角地布置到第二2x2阵列中。

    Differential pair connection arrangement, and method and computer program product for making same
    196.
    发明授权
    Differential pair connection arrangement, and method and computer program product for making same 有权

    公开(公告)号：US07441222B2

    公开(公告)日：2008-10-21

    申请号：US11540082

    申请日：2006-09-29

    Applicant: Neel Mathews

    Inventor： Neel Mathews

    IPC: H03K5/22

    CPC classification number: G06F17/5068 ,  G06F17/5077 ,  H05K1/0245 ,  H05K1/111 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/0979 ,  H05K2201/10689

    Abstract: Disclosed is a connection arrangement for connecting end portions of differential pairs to pads. In the arrangement, first and second signal traces comprising the differential pair are formed in first and second layers, respectively, of a printed circuit board. Each of the signal traces has a run portion and an end portion. The end portions of the first and second signal traces are connected, respectively, to first and second pads. At the beginning of the end portions in a region of the printed circuit board on a first lateral side of the first pad both the first and second signal traces split into two branches. One branch each from the first and second signal traces traverses a path around a top side of the first pad and the remaining branches from the first and second signal traces traverse a path around the bottom side of the first pad. The branches of the first and second signal traces come together again in a region of the printed circuit board on a second lateral side of the first pad. A terminal portion of the first signal trace extends away from the region where the two branches of the first signal trace come together again and contacts the first pad. A terminal portion of the second signal trace extends away from the region where the two branches of the second signal trace come together again in a direction away from the first pad and towards the second pad, and contacts the second pad. A projection of the run and branch portions of the second signal trace in a plane of the first layer overlaps the run and branch portions of first signal trace up to the point where the branches come together again.

    Display device including wiring board
    197.
    发明申请
    Display device including wiring board 审中-公开
    显示设备包括接线板

    公开(公告)号：US20080186293A1

    公开(公告)日：2008-08-07

    申请号：US11902464

    申请日：2007-09-21

    Applicant: Kazuaki Igarashi ,  Hirokazu Okamoto

    Inventor： Kazuaki Igarashi ,  Hirokazu Okamoto

    IPC: G09G3/00

    CPC classification number: G09G3/3611 ,  H05K1/147 ,  H05K1/181 ,  H05K3/361 ,  H05K2201/052 ,  H05K2201/09227 ,  H05K2201/09254

    Abstract: A display device includes a display panel including a display area, a first driving IC chip and a second driving IC chip, which are disposed with an interval along an end edge of the display panel, a cascade wiring line which connects the first driving IC chip and the second driving IC chip on the display panel, and a wiring board with a comb-shaped end portion having a first projection portion and a second projection portion, the wiring board being connected to the display panel such that the first projection portion and the second projection portion are electrically connected to the first driving IC chip and the second driving IC chip, with the cascade wiring line being interposed between the first projection portion and the second projection portion, wherein the cascade wiring line is exposed from the wiring board.

    Abstract translation: 显示装置包括：显示面板，包括显示区域，第一驱动IC芯片和第二驱动IC芯片，其沿着显示面板的端部边缘设置间隔;级联布线，其将第一驱动IC芯片 和显示面板上的第二驱动IC芯片，以及具有梳状端部的布线板，具有第一突出部和第二突出部，所述布线板与显示面板连接，使得第一突出部和 第二突起部分电连接到第一驱动IC芯片和第二驱动IC芯片，其中级联布线插入在第一突出部分和第二突出部分之间，其中级联布线从布线板露出。

    Differential pair connection arrangement, and method and computer program product for making same
    198.
    发明申请
    Differential pair connection arrangement, and method and computer program product for making same 有权
    差分对连接布置，方法和计算机程序产品相同

    公开(公告)号：US20080082950A1

    公开(公告)日：2008-04-03

    申请号：US11540082

    申请日：2006-09-29

    Applicant: Neel Mathews

    Inventor： Neel Mathews

    IPC: G06F17/50 ,  H03K17/693

    CPC classification number: G06F17/5068 ,  G06F17/5077 ,  H05K1/0245 ,  H05K1/111 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/0979 ,  H05K2201/10689

    Abstract: Disclosed is a connection arrangement for connecting end portions of differential pairs to pads. In the arrangement, first and second signal traces comprising the differential pair are formed in first and second layers, respectively, of a printed circuit board. Each of the signal traces has a run portion and an end portion. The end portions of the first and second signal traces are connected, respectively, to first and second pads. At the beginning of the end portions in a region of the printed circuit board on a first lateral side of the first pad both the first and second signal traces split into two branches. One branch each from the first and second signal traces traverses a path around a top side of the first pad and the remaining branches from the first and second signal traces traverse a path around the bottom side of the first pad. The branches of the first and second signal traces come together again in a region of the printed circuit board on a second lateral side of the first pad. A terminal portion of the first signal trace extends away from the region where the two branches of the first signal trace come together again and contacts the first pad. A terminal portion of the second signal trace extends away from the region where the two branches of the second signal trace come together again in a direction away from the first pad and towards the second pad, and contacts the second pad. A projection of the run and branch portions of the second signal trace in a plane of the first layer overlaps the run and branch portions of first signal trace up to the point where the branches come together again.

    Abstract translation: 公开了用于将差分对的端部连接到焊盘的连接装置。 在该布置中，包括差分对的第一和第二信号迹线分别形成在印刷电路板的第一和第二层中。 每个信号迹线具有一个运行部分和一个端部部分。 第一和第二信号迹线的端部分别连接到第一和第二焊盘。 在第一焊盘的第一横向侧的印刷电路板的区域的端部的开始处，第一和第二信号迹线分成两个分支。 每个来自第一和第二信号迹线的一个分支穿过围绕第一焊盘的顶侧的路径，并且来自第一和第二信号迹线的剩余分支遍及第一焊盘的底侧周围的路径。 第一和第二信号迹线的分支再次位于印刷电路板的位于第一焊盘的第二侧面的区域中。 第一信号迹线的终端部分远离第一信号迹线的两个分支再次聚集并接触第一焊盘的区域。 第二信号迹线的终端部分远离第二信号迹线的两个分支再次沿远离第一焊盘的方向并朝向第二焊盘的区域延伸，并接触第二焊盘。 在第一层的平面中第二信号迹线的行程和分支部分的投影与第一信号迹线的行程和分支部分重叠，直到分支再次聚集在一起。

    Circuit board
    200.
    发明申请
    Circuit board 审中-公开
    电路板

    公开(公告)号：US20070236086A1

    公开(公告)日：2007-10-11

    申请号：US11715962

    申请日：2007-03-09

    Applicant: Ayako Takagi

    Inventor： Ayako Takagi

    IPC: H02J3/00 ,  H02J1/10

    CPC classification number: H05K1/147 ,  H05K1/0216 ,  H05K1/0237 ,  H05K1/142 ,  H05K1/148 ,  H05K2201/09236 ,  H05K2201/09254 ,  Y10T307/25 ,  Y10T307/50

    Abstract: A transmitter IC is disposed on a first substrate. The transmitter IC supplies a pair of differential signals. A pair of bus lines is disposed on the first substrate. The pair of bus lines has each connection to receive the pair of differential signals. A terminating register is disposed on the first substrate. The terminating register is electrically connected to one end of the pair of bus lines. N pairs of first branch lines are disposed on the first substrate. Each of the N pairs of first branch lines is branched from the pair of bus lines. N pairs of second branch lines are disposed on a second substrate. Each of the N pairs of second branch lines is electrically connected to each of the N pairs of first branch lines. N units of receiver ICs are disposed on a third substrate. Each of the N units of receiver ICs is electrically connected to each of the N pairs of second branch lines. Relationship between a common mode impedance Z1 of the first branch lines and a common mode impedance Z2 of the second branch lines is 0.8·Z1≦Z2≦1.2·Z1.

    Abstract translation: 发射器IC设置在第一基板上。 发射机IC提供一对差分信号。 一对总线布置在第一基板上。 该对总线线路具有接收一对差分信号的每个连接。 终端寄存器设置在第一基板上。 终端寄存器电连接到该对总线线路的一端。 N对第一分支线设置在第一基板上。 N对第一分支线中的每一对从一对总线分支。 N对第二分支线设置在第二基板上。 N对第二分支线中的每一对电连接到N对第一分支线中的每一对。 接收器IC的N个单元设置在第三基板上。 接收器IC的N个单元中的每一个电连接到N对第二分支线中的每一个。 第一支线的共模阻抗Z 1与第二支线的共模阻抗Z 2之间的关系为0.8.Z 1 <= Z 2 <= 1.2.Z 1。

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