公开(公告)号：US20100248506A1

公开(公告)日：2010-09-30

申请号：US12410095

申请日：2009-03-24

Applicant: Mark Kenneth Hoffmeyer ,  Steven Paul Ostrander ,  Sri M. Sri-Jayantha

Inventor： Mark Kenneth Hoffmeyer ,  Steven Paul Ostrander ,  Sri M. Sri-Jayantha

IPC: H01R12/00 ,  H01R43/04

CPC classification number: H05K1/111 ,  H01R43/0256 ,  H05K3/3421 ,  H05K2201/0373 ,  H05K2201/09736 ,  H05K2201/2036 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/49218

Abstract: A method and a surface mount technology (SMT) pad structure are provided for implementing enhanced solder joint robustness. The SMT pad structure includes a base SMT pad. The base SMT pad receives a connector for soldering to the SMT pad structure. A standoff structure having a selected geometry is defined on the base SMT pad to increase thickness of the solder joint for the connector.

Abstract translation: 提供了一种方法和表面贴装技术（SMT）焊盘结构，用于实现增强的焊点鲁棒性。 SMT焊盘结构包括基板SMT焊盘。 基座SMT焊盘接收用于焊接到SMT焊盘结构的连接器。 在基座SMT焊盘上限定具有选定几何形状的间隔结构，以增加用于连接器的焊点的厚度。

公开(公告)号：US20100242271A1

公开(公告)日：2010-09-30

申请号：US12785037

申请日：2010-05-21

Applicant: Yasuhiko Inui ,  Takamichi Ogawa ,  Seiji Ichiyanagi ,  Jun Otsuka ,  Manabu Sato

Inventor： Yasuhiko Inui ,  Takamichi Ogawa ,  Seiji Ichiyanagi ,  Jun Otsuka ,  Manabu Sato

IPC: H05K3/00

CPC classification number: H05K1/162 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/092 ,  H05K3/4644 ,  H05K2201/0175 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09718 ,  H05K2201/09736 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/4981 ,  Y10T407/1946 ,  Y10T407/1948 ,  H01L2924/00

Abstract: A dielectric structure including a metal foil, a dielectric layer and a conductor layer provided in this order, wherein the metal foil has a thickness of from 10 to 40 μm, the dielectric layer has a thickness of from 0.3 to 5 μm, and the conductor layer has a thickness of from 0.3 to 10 μm. The dielectric structure has plural vias which are separated from each other, and which penetrate through both of the dielectric layer and the conductor layer. The vias of the dielectric layer have different diameters which are in a range of from 100 to 300 μm, a diameter of each of the vias of the conductor layer is larger than a diameter of a corresponding via of the dielectric layer by 5 to 50 μm, and a minimum via pitch is from 100 to 350 μm.

Abstract translation: 包括依次设置的金属箔，电介质层和导体层的电介质结构体，其中金属箔的厚度为10〜40μm，电介质层的厚度为0.3〜5μm，导体 层的厚度为0.3〜10μm。 电介质结构具有彼此分离并且穿透介电层和导体层两者的多个通孔。 电介质层的通孔具有不同的直径，范围为100〜300μm，导体层的通孔的直径大于电介质层的通孔的直径为5〜50μm ，最小通孔间距为100〜350μm。

公开(公告)号：US20100236822A1

公开(公告)日：2010-09-23

申请号：US12498860

申请日：2009-07-07

Applicant: Toshiki FURUTANI ,  Takeshi FURUSAWA

Inventor： Toshiki FURUTANI ,  Takeshi FURUSAWA

IPC: H05K1/18 ,  H05K3/30

CPC classification number: H01L21/4857 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L2224/16 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K1/111 ,  H05K1/187 ,  H05K3/205 ,  H05K3/243 ,  H05K3/244 ,  H05K3/428 ,  H05K3/4652 ,  H05K2201/0949 ,  H05K2201/0969 ,  H05K2201/09736 ,  H05K2201/09745 ,  H05K2201/10674 ,  Y10T29/4913 ,  H01L2224/0401

Abstract: A wiring board is formed with a substrate, conductive patterns laminated in the thickness direction of the substrate, multiple pads having a predetermined pitch and formed on the same layer as the conductive patterns, a conductive bonding layer arranged on each of the multiple pads, and an electronic component having electrodes. Here, the electronic component is arranged inside the substrate. The electrodes of the electronic component and the multiple pads are electrically connected to each other by means of bonding layers. Also, the height of each of the multiple pads is greater than the height of the conductive pattern adjacent to each pad. Moreover, a protective material related to the bonding layers is not formed at least on the layer where the pads and the first conductive patterns are formed.

Abstract translation: 布线板形成有基板，在基板的厚度方向上层叠的导电图案，具有预定间距的多个焊盘，并形成在与导电图案相同的层上，布置在多个焊盘的每一个上的导电接合层，以及 具有电极的电子部件。 这里，电子部件配置在基板的内部。 电子部件的电极和多个焊盘通过接合层彼此电连接。 此外，多个焊盘中的每一个的高度大于与每个焊盘相邻的导电图案的高度。 此外，至少在形成焊盘和第一导电图案的层上形成与结合层相关的保护材料。

公开(公告)号：US07800216B2

公开(公告)日：2010-09-21

申请号：US10565078

申请日：2005-02-03

Applicant: Yasushi Inagaki ,  Katsuyuki Sano

Inventor： Yasushi Inagaki ,  Katsuyuki Sano

IPC: H01L23/14

CPC classification number: H01L23/66 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/81 ,  H01L2223/6616 ,  H01L2223/6622 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/351 ,  H05K1/056 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/4641 ,  H05K2201/0352 ,  H05K2201/09536 ,  H05K2201/09736 ,  H05K2201/098 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: An IC chip for a high frequency region, particularly, a packaged substrate in which no malfunction or error occurs even if 3 GHz is exceeded. A conductive layer is formed at a thickness of 30 μm on a core substrate and a conductive circuit on an interlayer resin insulation layer is formed at a thickness of 15 μm. By thickening the conductive layer, the volume of the conductor itself can be increased thereby decreasing its resistance. Further, by using the conductive layer as a power source layer, the capacity of supply of power to an IC chip can be improved.

Abstract translation: 一种用于高频区域的IC芯片，特别是即使超过3GHz也不发生故障或错误的封装衬底。 在芯基板上形成厚度为30μm的导电层，在层间树脂绝缘层上形成厚度为15μm的导电电路。 通过增厚导电层，导体本身的体积可以增加，从而减小其电阻。 此外，通过使用导电层作为电源层，可以提高向IC芯片供电的能力。

公开(公告)号：US20100218983A1

公开(公告)日：2010-09-02

申请号：US12685731

申请日：2010-01-12

Applicant: Toru Furuta ,  Kotaro Takagi ,  Michio Ido ,  Akihiro Miyata ,  Fumitaka Takagi

Inventor： Toru Furuta ,  Kotaro Takagi ,  Michio Ido ,  Akihiro Miyata ,  Fumitaka Takagi

IPC: H05K1/09 ,  C23F1/00 ,  B05D5/12 ,  H05K1/11

CPC classification number: C23F1/02 ,  H01L21/4846 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49866 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H05K3/108 ,  H05K3/243 ,  H05K3/4007 ,  H05K3/4644 ,  H05K2201/0367 ,  H05K2201/09736 ,  H05K2203/0369 ,  H05K2203/049 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A method for manufacturing a printed wiring board includes forming a metal film on a surface of an insulative board, a plating resist on the metal film, and a plated-metal film on the metal film exposed from the plating resist, covering a portion of the plated-metal film with an etching resist, etching to reduce thickness of the plated-metal film exposed from the etching resist, removing the etching and plating resists, and forming a wiring having a pad for wire-bonding an electrode of an electronic component and a conductive circuit thinner than the pad by removing the metal film exposed after the plating resist is removed, a solder-resist layer on the surface of the board and wiring, an opening in the layer exposing the pad and a portion of the circuit contiguous to the pad, and a metal coating on the pad and portion of the circuit exposed through the opening.

Abstract translation: 一种制造印刷电路板的方法，包括在绝缘板的表面上形成金属膜，在金属膜上形成电镀抗蚀剂，以及在电镀抗蚀剂暴露的金属膜上的镀金属膜，覆盖一部分 具有抗蚀剂的电镀金属膜，蚀刻以减少从抗蚀剂暴露的电镀金属膜的厚度，去除蚀刻和电镀抗蚀剂，以及形成具有用于将电子部件的电极引线接合的焊盘的布线，以及 通过去除在电镀抗蚀剂之后暴露的金属膜而比焊盘更薄的导电电路被去除，在该板和布线的表面上的阻焊层，暴露该焊盘的该层中的一个开口和该电路的一部分与 焊盘和焊盘上的金属涂层以及通过开口露出的电路部分。

公开(公告)号：US20100218980A1

公开(公告)日：2010-09-02

申请号：US12582050

申请日：2009-10-20

Applicant: Toru Furuta ,  Kotaro Takagi ,  Michio Ido ,  Fumitaka Takagi

Inventor： Toru Furuta ,  Kotaro Takagi ,  Michio Ido ,  Fumitaka Takagi

IPC: H05K1/09 ,  H05K1/11

CPC classification number: H05K1/111 ,  H01L2224/16225 ,  H01L2224/73204 ,  H05K3/108 ,  H05K3/243 ,  H05K3/323 ,  H05K3/4602 ,  H05K2201/0949 ,  H05K2201/09736 ,  H05K2201/10674 ,  H05K2203/0369 ,  H05K2203/0574 ,  Y02P70/611

Abstract: A printed wiring board has an insulative board having a first surface and a second surface on the opposite side of the first surface, a wiring formed on the first surface of the insulative board and having a pad and a conductive circuit contiguous to the pad, and a metal film formed on the pad. The pad is provided to mount an electronic component having a gold bump. The pad has a thickness which is greater than a thickness of the conductive circuit.

Abstract translation: 印刷电路板具有绝缘板，其具有在第一表面的相对侧上的第一表面和第二表面，在绝缘板的第一表面上形成的布线，并具有与该焊盘相邻的焊盘和导电电路，以及 形成在垫上的金属膜。 提供垫以安装具有金凸块的电子部件。 焊盘的厚度大于导电电路的厚度。

公开(公告)号：US07733665B2

公开(公告)日：2010-06-08

申请号：US11431572

申请日：2006-05-11

Applicant: Toshikazu Harada ,  Kouji Kondo

Inventor： Toshikazu Harada ,  Kouji Kondo

IPC: H05K1/11

CPC classification number: H05K3/4688 ,  H01L2924/0002 ,  H05K1/0237 ,  H05K1/0265 ,  H05K1/036 ,  H05K3/382 ,  H05K3/4617 ,  H05K3/4632 ,  H05K2201/0129 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/09736 ,  H01L2924/00

Abstract: A multi-layer substrate connecting to an external electric device includes: a plurality of resin films; and a plurality of conductive patterns. The resin films are stacked together with the conductive patterns. The conductive pattern includes an inner conductive pattern and a surface conductive pattern. The inner conductive pattern is disposed inside of the multi-layer substrate for providing an inner circuit. The surface conductive pattern is exposed on the multi-layer substrate for connecting to the external electric device. The surface conductive pattern has a thickness in a stacking direction, which is thicker than a thickness of the inner conductive pattern.

Abstract translation: 连接到外部电气装置的多层基板包括：多个树脂膜; 和多个导电图案。 树脂膜与导电图案堆叠在一起。 导电图案包括内导电图案和表面导电图案。 内部导电图案设置在多层基板的内部，用于提供内部电路。 表面导电图案暴露在多层基板上，用于连接外部电气装置。 表面导电图案的层叠方向的厚度比内部导电图案的厚度厚。

公开(公告)号：US07714452B2

公开(公告)日：2010-05-11

申请号：US11847776

申请日：2007-08-30

Applicant: Lawrence A. Clevenger ,  Mukta Ghate Farooq ,  Louis Lu-Chen Hsu ,  William Francis Landers ,  Donna S. Zupanski-Nielson ,  Carl John Radens ,  Chih-Chao Yang

Inventor： Lawrence A. Clevenger ,  Mukta Ghate Farooq ,  Louis Lu-Chen Hsu ,  William Francis Landers ,  Donna S. Zupanski-Nielson ,  Carl John Radens ,  Chih-Chao Yang

IPC: H01L23/48 ,  H01L23/52 ,  H01L21/44

CPC classification number: H05K3/3436 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/12 ,  H01L24/17 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/06102 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/1403 ,  H01L2224/49109 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H05K2201/094 ,  H05K2201/09736 ,  H05K2201/09845 ,  Y02P70/613 ,  H01L2224/29099 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An electrical structure and method comprising a first substrate electrically and mechanically connected to a second substrate. The first substrate comprises a first electrically conductive pad and a second electrically conductive pad. The second substrate comprises a third electrically conductive pad, a fourth electrically conductive pad, and a first electrically conductive member. The fourth electrically conductive pad comprises a height that is different than a height of the first electrically conductive member. The electrically conductive member is electrically and mechanically connected to the fourth electrically conductive pad. A first solder ball connects the first electrically conductive pad to the third electrically conductive pad. The first solder ball comprises a first diameter. A second solder ball connects the second electrically conductive pad to the first electrically conductive member. The second solder ball comprises a second diameter. The first diameter is greater than said second diameter.

Abstract translation: 一种电结构和方法，包括电和机械地连接到第二衬底的第一衬底。 第一基板包括第一导电焊盘和第二导电焊盘。 第二基板包括第三导电焊盘，第四导电焊盘和第一导电部件。 第四导电焊盘包括与第一导电构件的高度不同的高度。 导电构件电连接和机械地连接到第四导电垫。 第一焊球将第一导电焊盘连接到第三导电焊盘。 第一焊球包括第一直径。 第二焊球将第二导电焊盘连接到第一导电构件。 第二焊球包括第二直径。 第一直径大于所述第二直径。

公开(公告)号：US07714232B2

公开(公告)日：2010-05-11

申请号：US10588467

申请日：2005-02-18

Applicant: Yusuke Igarashi ,  Sadamichi Takakusaki ,  Motoichi Nezu ,  Takaya Kusabe

Inventor： Yusuke Igarashi ,  Sadamichi Takakusaki ,  Motoichi Nezu ,  Takaya Kusabe

IPC: H05K1/16

CPC classification number: H01L23/49531 ,  H01L21/4846 ,  H01L21/565 ,  H01L23/4334 ,  H01L23/49811 ,  H01L24/48 ,  H01L24/97 ,  H01L25/16 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12041 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30105 ,  H05K1/0203 ,  H05K1/0265 ,  H05K1/056 ,  H05K3/06 ,  H05K3/284 ,  H05K2201/0355 ,  H05K2201/09736 ,  H05K2203/0369 ,  H05K2203/1476 ,  Y10T29/49139 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: Provided are a hybrid integrated circuit device in which fine patterns can be formed while current-carrying capacitances are ensured, and a method of manufacturing the same. The hybrid integrated circuit device of the present invention includes conductive patterns formed on a front surface of a circuit substrate and circuit elements electrically connected respectively to the conductive patterns. The conductive patterns include a first conductive pattern and a second conductive pattern formed more thickly than the first conductive pattern. The second conductive pattern includes a protruding portion protruding in a thickness direction thereof.

Abstract translation: 提供一种混合集成电路器件及其制造方法，其中可以形成精细图案，同时确保载流电容。 本发明的混合集成电路装置包括形成在电路基板的前表面上的导电图案和分别电连接到导电图案的电路元件。 导电图案包括比第一导电图案更厚的第一导电图案和第二导电图案。 第二导电图案包括在其厚度方向上突出的突出部分。

公开(公告)号：US07696613B2

公开(公告)日：2010-04-13

申请号：US11515803

申请日：2006-09-06

Applicant: Junichi Nakamura ,  Kinji Nagata

Inventor： Junichi Nakamura ,  Kinji Nagata

IPC: H01L23/04 ,  H01L23/498 ,  H01L23/12 ,  B32B25/10 ,  H05K3/46 ,  H05K1/02

CPC classification number: H05K3/4682 ,  H01L23/49822 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/01078 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0265 ,  H05K3/205 ,  H05K3/423 ,  H05K2201/0352 ,  H05K2201/09736 ,  H05K2203/0733

Abstract: A multilayered wiring substrate is constructed by stacking wiring layers 105, 108, 110, 112 and insulating layers 104, 106, 107, 109 in predetermined number, with at least one of the wiring layers being formed as a reinforcing wiring layer 103 whose thickness is 35 to 150 μm arranged in one layer or plural layers. Also, the thickness of the reinforcing wiring layer is larger than that of the other wiring layers.

Abstract translation: 多层布线基板通过以预定数量层叠布线层105,108,110,112和绝缘层104,106,107,109而构成，其中布线层中的至少一个形成为加强布线层103，其厚度为 35〜150μm排列成一层或多层。 此外，增强布线层的厚度大于其它布线层的厚度。