公开(公告)号：US08581395B2

公开(公告)日：2013-11-12

申请号：US13523464

申请日：2012-06-14

Applicant: Shinji Moriyama ,  Tomio Yamada

Inventor： Shinji Moriyama ,  Tomio Yamada

IPC: H01L23/34 ,  H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/28

CPC classification number: H01L23/13 ,  H01L23/10 ,  H01L23/3121 ,  H01L23/3677 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/50 ,  H01L23/66 ,  H01L24/48 ,  H01L24/73 ,  H01L25/165 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3025 ,  H03G3/3042 ,  H05K1/0263 ,  H05K1/141 ,  H05K1/183 ,  H05K3/3405 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/099 ,  H05K2201/09909 ,  H05K2201/10371 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A hybrid integrated circuit device having high mount reliability includes a module substrate which is a ceramic wiring substrate, a plurality of electronic component parts laid out on the main surface of the module substrate, a plurality of electrode terminals laid out on the rear surface of the module substrate, and a cap which is fixed to the module substrate to cover the main surface of the module substrate. The electrode terminals include ones which are aligned along the edges of the module substrate and power voltage supply terminals which are located inner than these electrode terminals. The electrode terminals aligned along the substrate edges are coated, at least in their portions close to the substrate edge, with a protection film having a thickness of several tens micrometers or less. Connection reinforcing terminals consist of a plurality of divided terminals which are independent of each other, and are ground terminals.

Abstract translation: 具有高安装可靠性的混合集成电路装置包括：作为陶瓷布线基板的模块基板，布置在模块基板的主表面上的多个电子部件部件，布置在模块基板的背面上的多个电极端子 模块基板和固定到模块基板以覆盖模块基板的主表面的盖。 电极端子包括沿着模块基板的边缘排列的电极端子和位于内部的电源电压端子。 沿着基板边缘排列的电极端子至少在其靠近基板边缘的部分中涂覆有几十微米或更小的厚度的保护膜。 连接加强端子由彼此独立的多个分开的端子组成，并且是接地端子。

公开(公告)号：US20130287935A1

公开(公告)日：2013-10-31

申请号：US13896351

申请日：2013-05-17

Applicant: Ngai Tsang ,  Kuo-Shu Kao

Inventor： Ngai Tsang ,  Kuo-Shu Kao

IPC: H05K3/02

CPC classification number: H05K3/02 ,  H05K1/0271 ,  H05K1/028 ,  H05K1/118 ,  H05K3/06 ,  H05K3/386 ,  H05K2201/0133 ,  H05K2201/0373 ,  H05K2201/09909

Abstract: A method of fabricating a circuit board is provided. An elastic bump material layer is formed on a substrate and then is patterned to form a plurality of first elastic bumps and a plurality of second elastic bumps, arranged in at least an array. A conductive layer is formed and then is patterned to form a patterned circuit layer to cover first plurality of elastic bumps and a portion of the substrate. An entirety of the plurality of second elastic bumps and another portion of the substrate are not covered by the patterned circuit layer. A protection layer is formed to cover a portion of the patterned circuit layer, a second number of the plurality of second elastic bumps entirely, a third number of the plurality of second elastic bumps partially and the another portion of the substrate, and expose the first number of the plurality of second elastic bumps.

Abstract translation: 提供一种制造电路板的方法。 在基板上形成弹性凸块材料层，然后将其图案化以形成至少排列成多个第一弹性凸块和多个第二弹性凸块。 形成导电层，然后将其图案化以形成图案化的电路层，以覆盖第一多个弹性凸块和基板的一部分。 多个第二弹性凸块和衬底的另一部分的整体未被图案化电路层覆盖。 保护层形成为覆盖图案化电路层的一部分，多个第二弹性凸块的第二数量，第二数量的多个第二弹性凸起部分和基板的另一部分，并且暴露第一 多个第二弹性凸块的数量。

公开(公告)号：US08510939B2

公开(公告)日：2013-08-20

申请号：US11924696

申请日：2007-10-26

Applicant: Robert J. Greenberg ,  Matthew J. McMahon ,  James Singleton Little ,  Kelly H. McClure ,  Brian V. Mech ,  Neil Hamilton Talbot ,  Jordan M. Neysmith

Inventor： Robert J. Greenberg ,  Matthew J. McMahon ,  James Singleton Little ,  Kelly H. McClure ,  Brian V. Mech ,  Neil Hamilton Talbot ,  Jordan M. Neysmith

IPC: H01K3/22

CPC classification number: A61N1/36046 ,  A61N1/0543 ,  A61N1/37223 ,  H05K1/028 ,  H05K1/0281 ,  H05K1/118 ,  H05K3/0014 ,  H05K3/28 ,  H05K2201/0133 ,  H05K2201/09018 ,  H05K2201/09145 ,  H05K2201/09909 ,  H05K2201/2009 ,  H05K2203/1105 ,  H05K2203/1476 ,  H05K2203/302 ,  Y10T29/49158

Abstract: Polymer materials are useful as electrode array bodies for neural stimulation. They are particularly useful for retinal stimulation to create artificial vision, cochlear stimulation to create artificial hearing, and cortical stimulation, and many related purposes. The pressure applied against the retina, or other neural tissue, by an electrode array is critical. Too little pressure causes increased electrical resistance, along with electric field dispersion. Too much pressure may block blood flow. Common flexible circuit fabrication techniques generally require that a flexible circuit electrode array be made flat. Since neural tissue is almost never flat, a flat array will necessarily apply uneven pressure. Further, the edges of a flexible circuit polymer array may be sharp and cut the delicate neural tissue. By applying the right amount of heat to a completed array, a curve can be induced. With a thermoplastic polymer it may be further advantageous to repeatedly heat the flexible circuit in multiple molds, each with a decreasing radius. Further, it is advantageous to add material along the edges. It is further advantageous to provide a fold or twist in the flexible circuit array. Additional material may be added inside and outside the fold to promote a good seal with tissue.

Abstract translation: 聚合物材料可用作神经刺激的电极阵列体。 它们特别有用于视网膜刺激以产生人造视觉，耳蜗刺激以产生人造听觉和皮质刺激以及许多相关目的。 通过电极阵列对视网膜或其他神经组织施加的压力是至关重要的。 太小的压力会导致电阻增加以及电场分散。 太大的压力可能会阻止血液流动。 通常的柔性电路制造技术通常需要使柔性电路电极阵列平坦。 由于神经组织几乎从不平坦，平面阵列必然会施加不均匀的压力。 此外，柔性电路聚合物阵列的边缘可以是尖锐的并切割精细的神经组织。 通过将适量的热应用于完整的阵列，可以引起曲线。 对于热塑性聚合物，可以进一步有利的是在多个模具中反复加热柔性电路，每个模具具有减小的半径。 此外，沿着边缘添加材料是有利的。 在柔性电路阵列中提供折叠或扭曲是更有利的。 可以在折叠内部和外部添加附加材料以促进与组织的良好密封。

公开(公告)号：US20130154130A1

公开(公告)日：2013-06-20

申请号：US13819983

申请日：2011-08-29

Applicant: Michael Peil ,  Florin Oswald ,  Harald Maiweg

Inventor： Michael Peil ,  Florin Oswald ,  Harald Maiweg

IPC: H01L33/54 ,  H01L31/0203

CPC classification number: H01L33/54 ,  F21K9/90 ,  F21Y2115/10 ,  H01L21/56 ,  H01L23/24 ,  H01L23/3121 ,  H01L27/1446 ,  H01L27/15 ,  H01L31/0203 ,  H01L31/02325 ,  H01L33/56 ,  H01L2924/0002 ,  H01L2933/005 ,  H05K1/0274 ,  H05K3/284 ,  H05K2201/0108 ,  H05K2201/0162 ,  H05K2201/0175 ,  H05K2201/09909 ,  H05K2201/10106 ,  H05K2201/10121 ,  H05K2201/10151 ,  H05K2203/0126 ,  H01L2924/00

Abstract: A method is provided for coating an optoelectronic chip-on-board module, including a flat substrate populated with one or more optoelectronic components, having a transparent, UV-resistant, and temperature-resistant coating made of one or more silicones. A corresponding optoelectronic chip-on-board module and a system having multiple optoelectronic chip-on-board modules are also provided. The method includes the following steps: a) preheating the substrate to be coated to a first temperature; b) applying on the preheated substrate a dam that encloses a surface area or partial area of the substrate to be coated, the dam being made of a first, heat-curable, highly reactive silicone that cures at the first temperature; c) filling the surface area or partial area of the substrate enclosed by the dam with a liquid second silicone; and d) curing the second silicone.

Abstract translation: 提供了一种用于涂覆光电芯片模块的方法，其包括具有一个或多个光电子部件的平坦基板，其具有由一个或多个硅氧烷构成的透明的耐紫外线和耐温涂层。 还提供了相应的光电芯片组模块和具有多个光电芯片模块的系统。 该方法包括以下步骤：a）将待涂覆的基材预热至第一温度; b）在预热的基底上施加包围待涂覆的基底的表面积或部分区域的坝，所述坝由在第一温度下固化的第一可热固化的高反应性硅树脂制成; c）用液体第二硅胶填充由大坝封闭的基板的表面积或部分区域; 和d）固化第二硅氧烷。

公开(公告)号：US08410536B2

公开(公告)日：2013-04-02

申请号：US13345227

申请日：2012-01-06

Applicant: John D. Prymak ,  Chris Stolarski ,  Alethia Melody ,  Antony P. Chacko ,  Gregory J. Dunn

Inventor： John D. Prymak ,  Chris Stolarski ,  Alethia Melody ,  Antony P. Chacko ,  Gregory J. Dunn

IPC: H01L27/108 ,  H01G4/005

CPC classification number: H05K1/162 ,  H01G9/012 ,  H01G9/042 ,  H01G9/045 ,  H01G9/15 ,  H05K3/429 ,  H05K2201/0329 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2201/09909 ,  H05K2203/0315 ,  Y10T29/417 ,  Y10T29/435

Abstract: A process for forming a laminate with capacitance and the laminate formed thereby. The process includes the steps of providing a substrate and laminating a conductive foil on the substrate wherein the foil has a dielectric. A conductive layer is formed on the dielectric. The conductive foil is treated to electrically isolate a region of conductive foil containing the conductive layer from additional conductive foil. A cathodic conductive couple is made between the conductive layer and a cathode trace and an anodic conductive couple is made between the conductive foil and an anode trace.

Abstract translation: 一种用于形成具有电容的叠层的方法和由此形成的层压体。 该方法包括以下步骤：提供衬底并将导电箔层压在衬底上，其中箔具有电介质。 在电介质上形成导电层。 处理导电箔以将包含导电层的导电箔的区域与另外的导电箔电隔离。 在导电层和阴极迹线之间形成阴极导电对，并且在导电箔和阳极迹线之间形成阳极导电耦合。

公开(公告)号：US08315064B2

公开(公告)日：2012-11-20

申请号：US13098764

申请日：2011-05-02

Applicant: Jeong Hyun Park

Inventor： Jeong Hyun Park

IPC: H05K7/00

CPC classification number: H05K3/4679 ,  H01L22/34 ,  H01L2924/0002 ,  H05K1/0268 ,  H05K3/4644 ,  H05K2201/0969 ,  H05K2201/09909 ,  Y10T29/49155 ,  Y10T29/49156 ,  H01L2924/00

Abstract: An apparatus for detecting pattern alignment error includes a first conductive pattern disposed over a first insulation member with a power source applied of the first conductive pattern; a second insulation member for covering the first conductive pattern; a second conductive pattern disposed on the second insulation member; a conductive via connected to the second conductive pattern and passing through the second insulation member; and an insulation pattern disposed in the first conductive pattern for detecting an alignment error in response to a position of the conductive via. The apparatus for detecting pattern alignment error can detect the alignment of lower wiring in a device with multi-layer wiring.

Abstract translation: 一种用于检测图案对准误差的装置包括：设置在第一绝缘构件上的第一导电图案，其中施加有第一导电图案的电源; 用于覆盖第一导电图案的第二绝缘构件; 布置在所述第二绝缘构件上的第二导电图案; 连接到第二导电图案并穿过第二绝缘构件的导电通孔; 以及设置在第一导电图案中的绝缘图案，用于响应于导电通孔的位置检测对准误差。 用于检测图案对准误差的装置可以检测具有多层布线的装置中的下布线的对准。

公开(公告)号：US08258888B2

公开(公告)日：2012-09-04

申请号：US12588731

申请日：2009-10-26

Applicant: Hidetaka Ootsuka

Inventor： Hidetaka Ootsuka

IPC: H01P5/02

CPC classification number: H05K1/117 ,  H05K1/0216 ,  H05K1/024 ,  H05K1/025 ,  H05K2201/0792 ,  H05K2201/09663 ,  H05K2201/09909 ,  H05K2201/10318 ,  Y10T29/49204

Abstract: A substrate device includes: a substrate; a ground layer disposed on one of two opposing surfaces of the substrate; a transmission line disposed on the other of the two opposing surfaces of the substrate; a pad which is disposed on the other of the two opposing surfaces of the substrate and connected to the transmission line; and a connector connected to the pad via a contact point. The pad has a part on the transmission line side and a part positioned on the opposite side of the transmission line with respect to the contact point with the connector which are electrically insulated from each other.

Abstract translation: 衬底装置包括：衬底; 设置在所述基板的两个相对表面中的一个上的接地层; 布置在所述基板的所述两个相对表面中的另一个表面上的传输线; 衬垫，其设置在所述衬底的所述两个相对表面中的另一个上并连接到所述传输线; 以及通过接触点连接到焊盘的连接器。 衬垫在传输线侧具有一部分，并且相对于彼此电绝缘的与连接器的接触点位于传输线相对侧的部分。

公开(公告)号：US08237532B2

公开(公告)日：2012-08-07

申请号：US12617002

申请日：2009-11-12

Applicant: Ryuji Takada

Inventor： Ryuji Takada

IPC: H01F5/00 ,  H01F27/02 ,  H01F27/28

CPC classification number: H01F27/022 ,  H01F17/04 ,  H01F27/2804 ,  H01F27/40 ,  H01F2027/2809 ,  H01F2027/2819 ,  H01L2924/0002 ,  H02M3/28 ,  H05K1/165 ,  H05K1/182 ,  H05K3/284 ,  H05K2201/0162 ,  H05K2201/086 ,  H05K2201/09909 ,  H05K2201/1003 ,  H05K2201/1034 ,  H05K2203/1316 ,  H05K2203/1322 ,  H01L2924/00

Abstract: An electronic circuit device 1 arranged with a first substrate 11, a core 33 (magnetic body) mounted on the first substrate 11, a resin sealing body 17 which covers the first substrate 11 and the core 33, and a curable type stress relieving material 35 which reduces stress applied to the core 33 by the resin sealing body 17 is arranged within the resin sealing body 33 from the side surface periphery of the core 33 across to the first substrate 11.

Abstract translation: 布置有第一基板11，安装在第一基板11上的芯33（磁体），覆盖第一基板11和芯33的树脂密封体17和可固化型应力释放材料35的电子电路装置1 通过树脂密封体17减少施加到芯33的应力，从树脂密封体33的芯部33的侧面周向配置到第一基板11。

公开(公告)号：US08222734B2

公开(公告)日：2012-07-17

申请号：US13306347

申请日：2011-11-29

Applicant: Shinji Moriyama ,  Tomio Yamada

Inventor： Shinji Moriyama ,  Tomio Yamada

IPC: H01L23/24 ,  H01L23/04 ,  H01L23/053 ,  H01L23/12 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/28

CPC classification number: H01L23/13 ,  H01L23/10 ,  H01L23/3121 ,  H01L23/3677 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/50 ,  H01L23/66 ,  H01L24/48 ,  H01L24/73 ,  H01L25/165 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3025 ,  H03G3/3042 ,  H05K1/0263 ,  H05K1/141 ,  H05K1/183 ,  H05K3/3405 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/099 ,  H05K2201/09909 ,  H05K2201/10371 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A hybrid integrated circuit device having high mount reliability includes a module substrate which is a ceramic wiring substrate, a plurality of electronic component parts laid out on the main surface of the module substrate, a plurality of electrode terminals laid out on the rear surface of the module substrate, and a cap which is fixed to the module substrate to cover the main surface of the module substrate. The electrode terminals include ones which are aligned along the edges of the module substrate and power voltage supply terminals which are located inner than these electrode terminals. The electrode terminals aligned along the substrate edges are coated, at least in their portions close to the substrate edge, with a protection film having a thickness of several tens micrometers or less. Connection reinforcing terminals consist of a plurality of divided terminals which are independent of each other, and are ground terminals.

Abstract translation: 具有高安装可靠性的混合集成电路装置包括：作为陶瓷布线基板的模块基板，布置在模块基板的主表面上的多个电子部件部件，布置在模块基板的背面上的多个电极端子 模块基板和固定到模块基板以覆盖模块基板的主表面的盖。 电极端子包括沿着模块基板的边缘排列的电极端子和位于内部的电源电压端子。 沿着基板边缘排列的电极端子至少在其靠近基板边缘的部分中涂覆有几十微米或更小的厚度的保护膜。 连接加强端子由彼此独立的多个分开的端子组成，并且是接地端子。

公开(公告)号：US08209859B2

公开(公告)日：2012-07-03

申请号：US12123733

申请日：2008-05-20

Applicant: Louis H. Feinstein

Inventor： Louis H. Feinstein

IPC: H05K3/30

CPC classification number: H05K3/284 ,  H05K2201/068 ,  H05K2201/0769 ,  H05K2201/09909 ,  H05K2201/10636 ,  H05K2201/10977 ,  H05K2203/0126 ,  Y02P70/611 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49171 ,  Y10T29/49227 ,  Y10T29/52 ,  Y10T29/53087 ,  Y10T29/53174 ,  Y10T29/53178

Abstract: A technique for processing an electronic apparatus (e.g., manufacturing an assembled circuit board, treating an assembled circuit board, etc.) involves applying encasement material to an area of the circuit board assembly while leaving at least a portion of the circuit board assembly exposed. The technique further involves causing the applied encasement material to harden (e.g., heating the encasement material in a curing oven, applying radiation, providing a chemical catalyst, etc.). Application and hardening of the encasement material may take place shortly after circuit board assembly (e.g., by automated equipment at a manufacturing facility in order to treat newly assembled boards) or at some later time in the field (e.g., by a technician servicing a legacy board).

Abstract translation: 一种用于处理电子设备（例如，制造组装电路板，处理组装电路板等）的技术涉及将外壳材料施加到电路板组件的区域，同时使电路板组件的至少一部分露出。 该技术还包括使所施加的包装材料硬化（例如，在固化炉中加热包装材料，施加辐射，提供化学催化剂等）。 封装材料的应用和硬化可能在电路板组装之后不久（例如，通过制造设施处的自动化设备来处理新组装的板）或在现场的某个稍后的时间（例如，由维护遗留物的技术人员） 板）。