公开(公告)号：US20170113925A1

公开(公告)日：2017-04-27

申请号：US15297662

申请日：2016-10-19

Applicant: Commissariat a L'Energie Atomique et aux Energies Alternatives

Inventor： Patrice REY

IPC: B81C1/00

CPC classification number: B81C1/0023 ,  B81C1/00333 ,  B81C2201/0108 ,  B81C2201/0109 ,  B81C2201/0126 ,  B81C2201/014 ,  B81C2201/056 ,  B81C2203/01 ,  B81C2203/0792

Abstract: Method for encapsulation of a microelectronic component, including making of a portion of sacrificial material on a front face of a first substrate in which the component is intended to be made, then making of a cover encapsulating the portion of sacrificial material, then making of the component by etching the first substrate from its back face, such that part of the component is arranged to face the portion of sacrificial material and such that the portion of sacrificial material is accessible from a back face of the component, then elimination of the portion of sacrificial material by etching from the back face of the component, then securing of the back face of the component to a second substrate.

公开(公告)号：US09586811B2

公开(公告)日：2017-03-07

申请号：US13157994

申请日：2011-06-10

Applicant: Chia-Hua Chu ,  Kuei-Sung Chang ,  Chung-Hsien Lin

Inventor： Chia-Hua Chu ,  Kuei-Sung Chang ,  Chung-Hsien Lin

IPC: H01L23/48 ,  B81B3/00 ,  B81B7/00 ,  B81C1/00

CPC classification number: B81B3/0005 ,  B81B3/001 ,  B81B7/007 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2207/012 ,  B81B2207/07 ,  B81B2207/092 ,  B81B2207/095 ,  B81B2207/096 ,  B81C1/00269 ,  B81C1/00579 ,  B81C2201/0111 ,  B81C2201/014 ,  B81C2201/0176 ,  B81C2203/0118 ,  B81C2203/019

Abstract: The present disclosure provides an embodiment of a micro-electro-mechanical system (MEMS) structure, the MEMS structure comprising a MEMS substrate; a first and second conductive plugs of a semiconductor material disposed on the MEMS substrate, wherein the first conductive plug is configured for electrical interconnection and the second conductive plug is configured as an anti-stiction bump; a MEMS device configured on the MEMS substrate and electrically coupled with the first conductive plug; and a cap substrate bonded to the MEMS substrate such that the MEMS device is enclosed therebetween.

Abstract translation: 本公开提供了微机电系统（MEMS）结构的实施例，所述MEMS结构包括MEMS基板; 设置在所述MEMS衬底上的半导体材料的第一和第二导电插塞，其中所述第一导电插头被配置用于电互连，所述第二导电插头被配置为抗静电凸块; 配置在所述MEMS基板上并与所述第一导电插塞电耦合的MEMS器件; 以及盖子衬底，其结合到MEMS衬底上，使得MEMS器件封装在其间。

公开(公告)号：US20170036905A1

公开(公告)日：2017-02-09

申请号：US15295997

申请日：2016-10-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Che Chen ,  Te-Yuan Wu ,  Chia-Huei Lin ,  Hui-Min Wu ,  Kun-Che Hsieh ,  Kuan-Yu Wang ,  Chung-Yi Chiu

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81B3/0075 ,  B81B2207/07 ,  B81C1/00246 ,  B81C1/00801 ,  B81C2201/014 ,  B81C2203/0714 ,  B81C2203/0735

Abstract: A MEMS structure includes a substrate, an inter-dielectric layer on a front side of the substrate, a MEMS component on the inter-dielectric layer, and a chamber disposed within the inter-dielectric layer and through the substrate. The chamber has an opening at a backside of the substrate. An etch stop layer is disposed within the inter-dielectric layer. The chamber has a ceiling opposite to the opening and a sidewall joining the ceiling. The sidewall includes a portion of the etch stop layer.

Abstract translation: MEMS结构包括衬底，在衬底的前侧上的介电层，介电层之间的MEMS组件，以及设置在介质间介质层内并通过衬底的室。 该腔室在衬底的背面具有开口。 蚀刻停止层设置在介电层内。 该室具有与开口相对的天花板和连接天花板的侧壁。 侧壁包括蚀刻停止层的一部分。

公开(公告)号：US09550669B2

公开(公告)日：2017-01-24

申请号：US13368370

申请日：2012-02-08

Applicant: Thoralf Kautzsch

Inventor： Thoralf Kautzsch

IPC: G01L9/00 ,  G01L9/16 ,  H01S4/00 ,  H01L21/336 ,  H01L21/311 ,  B81C1/00 ,  H04R19/00 ,  H04R31/00

CPC classification number: B81C1/00158 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81B2203/053 ,  B81C2201/014 ,  H04R19/005 ,  H04R31/00

Abstract: Embodiments related to pressure sensitive structures are described and depicted.

Abstract translation: 描述和描绘与压敏结构相关的实施例。

公开(公告)号：US20160332873A1

公开(公告)日：2016-11-17

申请号：US15223794

申请日：2016-07-29

Applicant: Infineon Technologies AG

Inventor： Andre Brockmeier ,  Christian Kalousek ,  Katharina Maier ,  Peter Zorn ,  Kai-Alexander Schreiber ,  Francesco Solazzi

IPC: B81C1/00 ,  B81C99/00

CPC classification number: B81C1/00619 ,  B32B37/0046 ,  B32B38/08 ,  B32B38/10 ,  B32B2457/14 ,  B81B7/008 ,  B81C1/0015 ,  B81C1/00238 ,  B81C1/00357 ,  B81C1/00492 ,  B81C99/0005 ,  B81C99/001 ,  B81C2201/0111 ,  B81C2201/0136 ,  B81C2201/014 ,  B81C2201/053 ,  B81C2203/0109 ,  B81C2203/031 ,  B81C2203/0735 ,  B81C2900/00 ,  Y10T156/15

Abstract: Methods, apparatuses and devices are described where a main wafer is irreversibly bonded to a carrier wafer and thinned to reduce a thickness of the main wafer, for example down to a thickness of 300 μm or below.

公开(公告)号：US20160304334A1

公开(公告)日：2016-10-20

申请号：US15097331

申请日：2016-04-13

Applicant: Robert Bosch GmbH

Inventor： Hans Artmann ,  Arnd Kaelberer ,  Christian Zielke ,  Oliver Breitschaedel ,  Peter Borwin Staffeld

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81C1/00182 ,  B81B2203/0118 ,  B81C2201/014

Abstract: A method for manufacturing microelectromechanical structures in a layer sequence and a corresponding electronic component having a microelectromechanical structure. The method includes provision of a carrier substrate including a first surface, an application of an insulation layer onto the first surface, an epitaxial growth of a first silicon layer onto the insulation layer, a structuring of the first silicon layer for forming trenches in the first silicon layer, a passivation of the first silicon layer, whereby the trenches are filled and a passivation layer is formed on a side facing away from the first surface, a structuring of the passivation layer, sacrificial areas and functional areas being formed in the first silicon layer, and the sacrificial areas are free of the passivation layer, at least at some points, on a side facing away from the carrier substrate, and, finally, removal of the sacrificial areas.

Abstract translation: 一种用于制造层序列中的微机电结构的方法和具有微机电结构的相应的电子部件。 该方法包括提供包括第一表面的载体衬底，在第一表面上施加绝缘层，将第一硅层外延生长到绝缘层上，第一硅层的结构用于在第一表面形成沟槽 硅层，所述第一硅层的钝化，由此所述沟槽被填充，并且在背离所述第一表面的一侧上形成钝化层，所述钝化层的结构化，在所述第一硅中形成的牺牲区域和功能区域 并且牺牲区域至少在某些点处，在背离载体衬底的一侧上没有钝化层，最后除去牺牲区域。

公开(公告)号：US09428381B2

公开(公告)日：2016-08-30

申请号：US14194912

申请日：2014-03-03

Applicant: Infineon Technologies AG

Inventor： Andre Brockmeier ,  Christian Griessler ,  Katharina Maier ,  Peter Zorn ,  Kai-Alexander Schreiber ,  Francesco Solazzi

IPC: B81C1/00 ,  B32B37/00 ,  B32B38/08 ,  B32B38/10 ,  B81B7/00 ,  B81C99/00

CPC classification number: B81C1/00619 ,  B32B37/0046 ,  B32B38/08 ,  B32B38/10 ,  B32B2457/14 ,  B81B7/008 ,  B81C1/0015 ,  B81C1/00238 ,  B81C1/00357 ,  B81C1/00492 ,  B81C99/0005 ,  B81C99/001 ,  B81C2201/0111 ,  B81C2201/0136 ,  B81C2201/014 ,  B81C2201/053 ,  B81C2203/0109 ,  B81C2203/031 ,  B81C2203/0735 ,  B81C2900/00 ,  Y10T156/15

Abstract: Methods, apparatuses and devices are described where a main wafer is irreversibly bonded to a carrier wafer and thinned to reduce a thickness of the main wafer, for example down to a thickness of 300 μm or below.

Abstract translation: 描述了方法，装置和装置，其中主晶片不可逆地结合到载体晶片并变薄以减小主晶片的厚度，例如降低至300μm或更小的厚度。

公开(公告)号：US09330907B2

公开(公告)日：2016-05-03

申请号：US14512158

申请日：2014-10-10

Applicant: The Board of Trustees of the Leland Stanford Junior University

Inventor： Robert Chen ,  James S. Harris, Jr. ,  Suyog Gupta

IPC: H01L21/02 ,  H01L21/00 ,  H01L29/161 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/06 ,  H01S5/34 ,  H01L21/3065 ,  B81C1/00 ,  H01S5/10

CPC classification number: H01L21/02535 ,  B81C1/00111 ,  B81C1/00571 ,  B81C2201/014 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/3065 ,  H01L29/0665 ,  H01L29/0676 ,  H01L29/161 ,  H01S5/1075 ,  H01S5/3427

Abstract: Suspended structures are provided using selective etch technology. Such structures can be protected on all sides when the selective undercut etch is performed, thereby providing excellent control of feature geometry combined with superior material quality.

公开(公告)号：US09190954B2

公开(公告)日：2015-11-17

申请号：US14219694

申请日：2014-03-19

Applicant: SEIKO EPSON CORPORATION

Inventor： Takahiko Yoshizawa

IPC: H03B5/30 ,  H01L21/768 ,  B81C1/00 ,  H03B5/32

CPC classification number: H03B5/30 ,  B81C1/00246 ,  B81C1/00801 ,  B81C2201/014 ,  B81C2203/0742 ,  B81C2203/0764 ,  H01L21/76802 ,  H03B5/32

Abstract: An electronic device according to an aspect of the invention include: a substrate; an underlayer having an opening and being formed on the substrate; a functional element provided on the underlayer; and a surrounding wall forming a cavity that accommodates the functional element, at least a part of the surrounding wall being disposed in the opening.

Abstract translation: 根据本发明的一个方面的电子设备包括：基板; 具有开口并形成在所述基板上的底层; 设置在底层上的功能元件; 以及形成容纳所述功能元件的空腔的周壁，所述周围壁的至少一部分设置在所述开口中。

公开(公告)号：US20150246809A1

公开(公告)日：2015-09-03

申请号：US14194912

申请日：2014-03-03

Applicant: Infineon Technologies AG

Inventor： Andre Brockmeier ,  Christian Griessler ,  Katharina Maier ,  Peter Zorn ,  Kai-Alexander Schreiber ,  Francesco Solazzi

IPC: B81C1/00 ,  B81C99/00 ,  B32B38/08 ,  B81B7/00 ,  B32B37/00 ,  B32B38/10

CPC classification number: B81C1/00619 ,  B32B37/0046 ,  B32B38/08 ,  B32B38/10 ,  B32B2457/14 ,  B81B7/008 ,  B81C1/0015 ,  B81C1/00238 ,  B81C1/00357 ,  B81C1/00492 ,  B81C99/0005 ,  B81C99/001 ,  B81C2201/0111 ,  B81C2201/0136 ,  B81C2201/014 ,  B81C2201/053 ,  B81C2203/0109 ,  B81C2203/031 ,  B81C2203/0735 ,  B81C2900/00 ,  Y10T156/15

Abstract: Methods, apparatuses and devices are described where a main wafer is irreversibly bonded to a carrier wafer and thinned to reduce a thickness of the main wafer, for example down to a thickness of 300 μm or below.

Abstract translation: 描述了方法，装置和装置，其中主晶片不可逆地结合到载体晶片并变薄以减小主晶片的厚度，例如降低至300μm或更小的厚度。