公开(公告)号：US08076588B2

公开(公告)日：2011-12-13

申请号：US12000730

申请日：2007-12-17

Applicant: Eiichi Hirakawa

Inventor： Eiichi Hirakawa

IPC: H05K1/11

CPC classification number: H05K1/0219 ,  H05K1/112 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09609 ,  H05K2201/09672 ,  H05K2201/10674

Abstract: A multilayer wiring board having a structure in which wiring layers 12A to 12D and insulating layers 11A to 11C are alternately arranged, and in which one or plural kinds of wirings selected from a group of a signal wiring 25 having a signal electrode 15, a power supply wiring 26 having a power supply electrode 16, and a ground wiring 27 having a ground electrode 17 are formed on each of the wiring layers 12A to 12D. The signal wiring 25 and the power supply wiring 26 are alternately provided on the insulating layers. Alternatively, the signal wiring 25 and the ground wiring 27 are alternately provided on the insulating layers.

Abstract translation: 具有布线层12A〜12D和绝缘层11A〜11C交替配置的结构的多层布线基板，其中从具有信号电极15的信号布线25的一组中选择一种或多种布线，功率 具有电源电极16的电源布线26和具有接地电极17的接地布线27形成在每个布线层12A至12D上。 信号布线25和电源布线26交替地设置在绝缘层上。 或者，信号布线25和接地布线27交替地设置在绝缘层上。

公开(公告)号：US07894204B1

公开(公告)日：2011-02-22

申请号：US12353341

申请日：2009-01-14

Applicant: Dave A. Mellick ,  Jerry L. Stevenson

Inventor： Dave A. Mellick ,  Jerry L. Stevenson

IPC: H05K1/18

CPC classification number: H05K1/14 ,  H05K1/0245 ,  H05K1/0289 ,  H05K2201/09609 ,  H05K2201/10303

Abstract: An assembly of connected circuit boards includes at least one each of a matrix board, an input board and an output board. There are two types of input board, one for hydrophone cable input and one for single-ended (SE) cable input. The matrix board provides for switching any pair of input differential signals to any channel on the output board.

Abstract translation: 连接电路板的组件包括矩阵板，输入板和输出板中的至少一个。 有两种类型的输入板，一种用于水听器电缆输入，一种用于单端（SE）电缆输入。 矩阵板用于将任何输入差分信号对转换到输出板上的任何通道。

公开(公告)号：US07793414B2

公开(公告)日：2010-09-14

申请号：US11642570

申请日：2006-12-20

Applicant: Belgacem Haba ,  Masud Beroz ,  David B. Tuckerman ,  Giles Humpston ,  Richard Dewitt Crisp

Inventor： Belgacem Haba ,  Masud Beroz ,  David B. Tuckerman ,  Giles Humpston ,  Richard Dewitt Crisp

IPC: H01R9/00 ,  H01R12/04

CPC classification number: H01L23/49838 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K1/115 ,  H05K3/041 ,  H05K3/06 ,  H05K3/202 ,  H05K3/4038 ,  H05K2201/09609 ,  H05K2201/097 ,  H05K2201/09827 ,  H05K2201/09881 ,  H05K2203/0733 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49165 ,  H01L2924/00

Abstract: Provided are connection structures for a microelectronic device and methods for forming the structure. A substrate is included having opposing surfaces and a plurality of holes extending through the surfaces. Also included is a plurality of electrically conductive posts. Each post extends from a base to a tip located within a corresponding hole of the substrate. An additional substrate may be provided such that the base of each post is located on a surface thereof. Additional electrically conductive posts may be provided having tips in corresponding holes of the additional substrate. Optionally, a dielectric material may be placed between the substrate and the posts.

Abstract translation: 提供了用于微电子器件的连接结构和用于形成结构的方法。 包括具有相对表面的基板和延伸穿过该表面的多个孔。 还包括多个导电柱。 每个柱从基部延伸到位于基板的相应孔内的尖端。 可以提供另外的基底，使得每个柱的基部位于其表面上。 可以提供额外的导电柱，其具有在附加衬底的相应孔中的尖端。 可选地，介电材料可以放置在基板和柱之间。

公开(公告)号：US07683266B2

公开(公告)日：2010-03-23

申请号：US11494744

申请日：2006-07-28

Applicant: Kiyoshi Shibata ,  Ryosuke Usui ,  Yasunori Inoue

Inventor： Kiyoshi Shibata ,  Ryosuke Usui ,  Yasunori Inoue

IPC: H01R12/04 ,  H05K1/11

CPC classification number: H05K3/445 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/01078 ,  H05K1/056 ,  H05K3/0047 ,  H05K3/44 ,  H05K2201/0382 ,  H05K2201/09054 ,  H05K2201/09609 ,  H05K2201/0969 ,  H05K2203/0323 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49165

Abstract: A circuit board and a circuit apparatus using the same which can prevent displacement and film exfoliation ascribable to thermal expansion, and suppress a drop in reliability at increasing temperatures. The circuit board of the circuit apparatus includes a metal substrate having pierced holes as a core member. Protrusions are formed on the top ends of the pierced holes, and depressions are formed in the bottom ends of the pierced holes. Wiring pattern layers are formed on both sides of this metal substrate via respective insulating layers. In order to establish electrical connection between the wiring pattern layers, a conductor layer which connects the wiring pattern layers is formed through the metal substrate via the pierced holes. The conductor layer thereby establishes electrical conduction between the wiring pattern layers. Furthermore, a semiconductor chip is directly connected to the surface side of the circuit board via solder balls.

Abstract translation: 一种电路板和使用该电路板的电路装置，其可以防止由于热膨胀而引起的位移和膜剥落，并且抑制在升高的温度下的可靠性降低。 电路装置的电路板包括具有穿孔作为芯构件的金属基板。 在穿孔的顶端形成突起，在穿孔的底端形成凹部。 接线图案层通过各自的绝缘层形成在该金属基板的两侧上。 为了建立布线图案层之间的电连接，通过穿孔穿过金属基板形成连接布线图案层的导体层。 导体层由此在布线图案层之间建立导电。 此外，半导体芯片通过焊球直接连接到电路板的表面侧。

公开(公告)号：US20100012367A1

公开(公告)日：2010-01-21

申请号：US11722342

申请日：2005-12-14

Applicant: Marc Andre De Samber ,  Koen Van Os

Inventor： Marc Andre De Samber ,  Koen Van Os

IPC: H05K1/11

CPC classification number: H05K1/0206 ,  H05K1/0263 ,  H05K2201/09509 ,  H05K2201/09609 ,  H05K2201/09627 ,  H05K2201/09672 ,  H05K2201/09781

Abstract: The present invention relates to a printed circuit board arrangement with a multi-layer substrate (1, 2) having a buried conductor (4) and a contact area (3), connected to the conductor (4) and being disposed on a surface of the substrate. In order to improve the cooling of the buried conductor, a metal cooling area (6) is provided above the conductor (4), and is connected to the conductor by means of one or more via conductors (7).

Abstract translation: 本发明涉及具有多层衬底（1,2）的印刷电路板装置，该多层衬底具有埋入导体（4）和与该导体（4）连接的接触区域（3） 底物。 为了改善掩埋导体的冷却，金属冷却区域（6）设置在导体（4）上方，并通过一个或多个通孔导体（7）与导体连接。

公开(公告)号：US20090189290A1

公开(公告)日：2009-07-30

申请号：US12020565

申请日：2008-01-27

Applicant: Karan Kacker ,  Douglas O. Powell ,  David L. Questad ,  David J. Russell ,  Sri M. Sri-Jayantha

Inventor： Karan Kacker ,  Douglas O. Powell ,  David L. Questad ,  David J. Russell ,  Sri M. Sri-Jayantha

IPC: H01L23/48 ,  H01L21/00

CPC classification number: H01L23/49827 ,  H01L23/498 ,  H01L23/49838 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05572 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/15151 ,  H01L2924/15311 ,  H05K1/0222 ,  H05K1/115 ,  H05K3/4602 ,  H05K2201/096 ,  H05K2201/09609 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/4919 ,  Y10T29/49204 ,  Y10T29/49222 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A substrate via structure for stacked vias in a substrate/chip assembly includes: a center via stack and a plurality of stacked vias clustered around the center via stack. In this structure, the center via and the surrounding vias are made of copper. Some of the surrounding vias may be non-functional vias and these may be of a different height than the functional vias.

Abstract translation: 用于衬底/芯片组件中的堆叠通孔的衬底通孔结构包括：中心通孔堆叠和多个堆叠的通孔，围绕中心通过堆叠聚集。 在这种结构中，中心通孔和周围的通孔由铜制成。 一些周围的通孔可以是非功能通孔，并且它们可以具有与功能通孔不同的高度。

公开(公告)号：US07528788B2

公开(公告)日：2009-05-05

申请号：US12174960

申请日：2008-07-17

Applicant: Gregory J. Dunn ,  Robert T. Croswell ,  George H. Kumpf ,  John A. Svigelj

Inventor： Gregory J. Dunn ,  Robert T. Croswell ,  George H. Kumpf ,  John A. Svigelj

IPC: H01Q3/40

CPC classification number: H01Q15/006 ,  H05K1/116 ,  H05K1/162 ,  H05K1/165 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2201/0715 ,  H05K2201/09509 ,  H05K2201/09609

Abstract: A high impedance surface (300) has a printed circuit board (302) with a first surface (314) and a second surface (316), and a continuous electrically conductive plate (319) disposed on the second surface (316) of the printed circuit board (302). A plurality of electrically conductive plates (318) is disposed on the first surface (314) of the printed circuit board (302), while a plurality of elements are also provided. Each element comprises at least one of (1) at least one multi-layer inductor (330, 331) electrically coupled between at least two of the electrically conductive plates (318) and embedded within the printed circuit board (302), and (2) at least one capacitor (320) electrically coupled between at least two of the electrically conductive plates (318). The capacitor (320) comprises at least one of (a) a dielectric material (328) disposed between adjacent electrically conductive plates, wherein the dielectric material (328) has a relative dielectric constant greater than 6, and (b) a mezzanine capacitor embedded within the printed circuit board (302).

Abstract translation: 高阻抗表面（300）具有带有第一表面（314）和第二表面（316）的印刷电路板（302）和设置在印刷的第二表面（316）上的连续导电板（319） 电路板（302）。 多个导电板（318）设置在印刷电路板（302）的第一表面（314）上，同时还提供多个元件。 每个元件包括（1）至少一个电耦合在至少两个导电板（318）之间并嵌入印刷电路板（302）内的多层电感器（330,331）中的至少一个，和（2 ）至少一个电耦合在至少两个导电板（318）之间的电容器（320）。 电容器（320）包括设置在相邻导电板之间的（a）介电材料（328）中的至少一个，其中介电材料（328）具有大于6的相对介电常数，以及（b）嵌入的夹层电容器 在印刷电路板（302）内。

公开(公告)号：US20090108465A1

公开(公告)日：2009-04-30

申请号：US12259811

申请日：2008-10-28

Applicant: Wiren D. Becker ,  Zhaoqing Chen ,  George Katopis

Inventor： Wiren D. Becker ,  Zhaoqing Chen ,  George Katopis

IPC: H01L23/52

CPC classification number: H05K1/0224 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2223/6622 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0219 ,  H05K1/0253 ,  H05K2201/09609 ,  H05K2201/09618 ,  H05K2201/09681 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  H01L2924/00

Abstract: Signal line conductors passing through vertical vias in an insulative substrate for supporting and interconnecting integrated circuit chips are provided with shielding conductors in adjacent vias that link respective power and ground planes. The shielding conductors' presence in positions around a signal via is made possible through the employment of power plane and ground plane conductive grids that are laid out in rhomboid patterns. The power plane and ground plane grids possess a left-right mirror relation to one another and are displaced to place the rhomboid's corners to avoid overlapping any of the grid lines.

公开(公告)号：US07495532B2

公开(公告)日：2009-02-24

申请号：US12009109

申请日：2008-01-16

Applicant: William E. McKinzie, III

Inventor： William E. McKinzie, III

IPC: H01P7/00

CPC classification number: H01P1/20 ,  H01P1/2005 ,  H05K1/0216 ,  H05K1/0236 ,  H05K1/0239 ,  H05K1/115 ,  H05K1/162 ,  H05K2201/09609 ,  H05K2201/09672

Abstract: Systems and methods are taught for blocking the propagation of electromagnetic waves in parallel-plate waveguide (PPW) structures. Periodic arrays of resonant vias are used to create broadband high frequency stop bands in the PPW, while permitting DC and low frequency waves to propagate. Some embodiments of resonant via arrays are mechanically balanced, which promotes improved manufacturability. Important applications include electromagnetic noise reduction in layered electronic devices such as circuit boards, ceramic modules, and semiconductor chips.

Abstract translation: 教导系统和方法阻止平行板波导（PPW）结构中电磁波的传播。 谐振通孔的周期阵列用于在PPW中产生宽带高频阻带，同时允许DC和低频波传播。 谐振通孔阵列的一些实施例是机械平衡的，这促进了改进的可制造性。 重要的应用包括诸如电路板，陶瓷模块和半导体芯片的分层电子设备中的电磁降噪。

公开(公告)号：US20090021887A1

公开(公告)日：2009-01-22

申请号：US12171204

申请日：2008-07-10

Applicant: Kousuke Nakamura ,  Takashi Masuda

Inventor： Kousuke Nakamura ,  Takashi Masuda

IPC: H01G4/30 ,  H01G9/00

CPC classification number: H01G4/30 ,  H01G4/005 ,  H01L2224/16225 ,  H05K1/112 ,  H05K1/162 ,  H05K3/4602 ,  H05K2201/09309 ,  H05K2201/096 ,  H05K2201/09609 ,  H05K2201/10674

Abstract: A capacitor capable of decoupling in a wide frequency band is obtained. A circuit in which capacitors having different capacitances are combined can be formed without increasing the number of components. Part of a first penetrating electrode or second penetrating electrode is cut by removing a cut portion. A penetrating electrode having a cut portion reduces the number of internal electrodes that are conductively connected, so that a capacitance to be extracted is small. The capacitance to be extracted can be adjusted, depending on which of layers of internal electrodes the cut portion is formed in.

Abstract translation: 可获得能够在宽频带中解耦的电容器。 可以在不增加组件数量的情况下形成其中组合具有不同电容的电容器的电路。 通过去除切割部分来切割第一穿透电极或第二穿透电极的一部分。 具有切割部分的穿透电极减少了导电连接的内部电极的数量，使得要提取的电容小。 可以根据形成切口部分的内部电极的哪一层来调节要提取的电容。