公开(公告)号：US20070052109A1

公开(公告)日：2007-03-08

申请号：US11320786

申请日：2005-12-30

Applicant: Chien-Fan Chen ,  Yi-Hsin Chen

Inventor： Chien-Fan Chen ,  Yi-Hsin Chen

IPC: H01L21/00

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L2224/05572 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2924/0001 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H05K3/3436 ,  H05K2201/0367 ,  Y02P70/613 ,  H01L2924/00014

Abstract: A flip-chip packaging process is disclosed. The present invention is featured in forming a copper pillar on a wafer, forming a solder on a substrate; and enabling the solder to substantially cover the entire externally-exposed surface of the copper pillar, thereby connecting the copper pillar to the substrate. The copper pillar of the present invention can be such as a prism or a cylinder.

Abstract translation: 公开了一种倒装芯片封装工艺。 本发明的特征在于在晶片上形成铜柱，在基板上形成焊料; 并且使得焊料能够基本上覆盖铜柱的整个外部暴露的表面，从而将铜柱连接到基板。 本发明的铜柱可以是棱镜或圆筒。

公开(公告)号：US20070013063A1

公开(公告)日：2007-01-18

申请号：US11533485

申请日：2006-09-20

Applicant: Viren Khandekar ,  Chunho Kim

Inventor： Viren Khandekar ,  Chunho Kim

IPC: H01L23/48

CPC classification number: H01L24/81 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/81136 ,  H01L2224/81141 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/303 ,  H05K3/3436 ,  H05K2201/0367 ,  H05K2201/09781 ,  H05K2203/048 ,  H05K2203/167 ,  Y02P70/613 ,  H01L2224/0401

Abstract: Some embodiments of the present invention relate to an electronic assembly that includes a substrate and a die. The electronic assembly further includes an alignment bump on one of the die and the substrate and a group of mating bumps on the other of the die and the substrate. The group of mating bumps is positioned such that if the alignment bump engages each of the mating bumps, the die is appropriately positioned relative to the substrate at that location where the alignment bump engages the group of mating bumps. In some embodiments, the alignment bump extends from the substrate while in other embodiments the alignment bump extends from the die. The alignment bump on the substrate (or die) may be part of a plurality of alignment bumps such that each alignment bump engages a different group of mating bumps on the die (or substrate).

Abstract translation: 本发明的一些实施例涉及一种包括基底和模具的电子组件。 所述电子组件还包括在所述管芯和所述衬底之一上的对准凸块和在所述管芯和所述衬底的另一个上的一组配合凸块。 该组配合凸块定位成使得如果对准凸块接合每个配合凸块，则该模具相对于该基板适当地定位在该位置处，该对准凸块与该组配合凸块接合。 在一些实施例中，对准突起从衬底延伸，而在其它实施例中，对准凸起从模具延伸。 衬底（或管芯）上的对准凸块可以是多个对准凸块的一部分，使得每个对准凸块与模具（或衬底）上的不同组的配合凸块接合。

公开(公告)号：US07161245B2

公开(公告)日：2007-01-09

申请号：US11216807

申请日：2005-08-31

Applicant: Atsushi Saito

Inventor： Atsushi Saito

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/563 ,  H01L24/10 ,  H01L24/13 ,  H01L24/29 ,  H01L24/83 ,  H01L24/90 ,  H01L33/62 ,  H01L2224/05001 ,  H01L2224/05124 ,  H01L2224/05548 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/83101 ,  H01L2224/83856 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0665 ,  H01L2924/12041 ,  H01L2924/14 ,  H05K3/305 ,  H05K3/325 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/068 ,  H05K2201/10977 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: An electronic component-mounted structure includes an electronic component having a bump electrode, the bump electrode including a projection made of a first resin and a conductive film covering at least a top of the projection; a substrate having a connecting terminal; and a second resin filling the space between the electronic component and the substrate, wherein the bump electrode abuts against the connecting terminal, and wherein the relationship T0

Abstract translation: 电子部件安装结构包括具有凸起电极的电子部件，所述凸起电极包括由第一树脂制成的突起和至少覆盖所述突起的顶部的导电膜; 具有连接端子的基板; 以及填充所述电子部件与所述基板之间的空间的第二树脂，其中所述凸起电极与所述连接端子抵接，并且其中满足所述关系T 0

公开(公告)号：US20060289200A1

公开(公告)日：2006-12-28

申请号：US11158044

申请日：2005-06-22

Applicant: Yu-Tuan Lee

Inventor： Yu-Tuan Lee

IPC: H05K1/18

CPC classification number: H05K3/4007 ,  H05K1/0306 ,  H05K3/386 ,  H05K3/4644 ,  H05K2201/0133 ,  H05K2201/0187 ,  H05K2201/0367 ,  H05K2201/09909 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49158

Abstract: A circuit board includes a substrate, an insulating layer, at least one protrusion, and a first circuit layer. The insulating layer is disposed on the substrate and has at least one protrusion-positioning region. At least a part of the protrusion is disposed on the protrusion-positioning region. The first circuit layer is disposed on the insulating layer and has at least one trace line extending onto the protrusion.

Abstract translation: 电路板包括基板，绝缘层，至少一个突起和第一电路层。 绝缘层设置在基板上并且具有至少一个突出定位区域。 突起的至少一部分设置在突起定位区域上。 第一电路层设置在绝缘层上并且具有延伸到突起上的至少一条迹线。

公开(公告)号：US20060286301A1

公开(公告)日：2006-12-21

申请号：US10571273

申请日：2004-09-10

Applicant: Kazuhiro Murata ,  Hiroshi Yokoyama ,  Daisuke Itoh ,  Akihito Izumitani ,  Noriaki Hata ,  Yosishige Matsuba

Inventor： Kazuhiro Murata ,  Hiroshi Yokoyama ,  Daisuke Itoh ,  Akihito Izumitani ,  Noriaki Hata ,  Yosishige Matsuba

IPC: B05D1/12 ,  B05D5/00 ,  B05D3/02

CPC classification number: B05D1/007 ,  B32B3/266 ,  B32B15/08 ,  H01L21/4867 ,  H01L2924/0002 ,  H05K3/125 ,  H05K3/245 ,  H05K3/4061 ,  H05K3/4647 ,  H05K2201/0367 ,  H05K2203/013 ,  H05K2203/105 ,  H05K2203/1131 ,  H05K2203/1476 ,  Y10T428/24322 ,  H01L2924/00

Abstract: A method of preparing substrates, including the steps of depositing metal particulates into a pillar form at a prescribed position of a substrate (1) by the use of a fine inkjet method, and then sintering the resultant to form a metal pillar (2).

Abstract translation: 一种制备衬底的方法，包括以下步骤：通过使用精细喷墨方法将基片（1）的规定位置的金属颗粒沉积成柱状，然后烧结所述金属柱（2）。

公开(公告)号：US07135771B1

公开(公告)日：2006-11-14

申请号：US11165144

申请日：2005-06-23

Applicant: Viren V. Khandekar ,  Chunho Kim

Inventor： Viren V. Khandekar ,  Chunho Kim

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/81 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/81136 ,  H01L2224/81141 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/303 ,  H05K3/3436 ,  H05K2201/0367 ,  H05K2201/09781 ,  H05K2203/048 ,  H05K2203/167 ,  Y02P70/613 ,  H01L2224/0401

Abstract: Some embodiments of the present invention relate to an electronic assembly that includes a substrate and a die. The electronic assembly further includes an alignment bump on one of the die and the substrate and a group of mating bumps on the other of the die and the substrate. The group of mating bumps is positioned such that if the alignment bump engages each of the mating bumps, the die is appropriately positioned relative to the substrate at that location where the alignment bump engages the group of mating bumps. In some embodiments, the alignment bump extends from the substrate while in other embodiments the alignment bump extends from the die. The alignment bump on the substrate (or die) may be part of a plurality of alignment bumps such that each alignment bump engages a different group of mating bumps on the die (or substrate).

公开(公告)号：US20060244140A1

公开(公告)日：2006-11-02

申请号：US11412310

申请日：2006-04-27

Applicant: Wen-Hung Hu

Inventor： Wen-Hung Hu

IPC: H01L23/48

CPC classification number: H05K3/28 ,  H01L21/4853 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05567 ,  H01L2224/1182 ,  H01L2224/11903 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/0041 ,  H05K3/108 ,  H05K3/243 ,  H05K3/4007 ,  H05K2201/0191 ,  H05K2201/0367 ,  H05K2203/025 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A conductive bump structure of a circuit board and a method for forming the same are proposed. A conductive layer is formed on an insulating layer on the surface of the circuit board. A first resist layer is formed on the conductive layer and a plurality of first openings is formed in the first resist layer to expose the conductive layer. Then, a patterned trace layer is electroplated in the first openings and a second resist layer is covered on the circuit board with the patterned trace layer. Second openings are formed in the second resist layer to expose part of the trace layer to be used as electrical connecting pads. Thereafter, metal bumps are electroplated in the second openings and the surface of the circuit board is covered with a solder mask. A thinning process is applied to the solder mask to expose the top surface of the metal bumps. Afterwards, an adhesive layer is formed on the surface of the metal bumps exposing out of the solder mask.

Abstract translation: 提出了一种电路板的导电凸块结构及其形成方法。 在电路板的表面上的绝缘层上形成导电层。 第一抗蚀剂层形成在导电层上，并且在第一抗蚀剂层中形成多个第一开口以暴露导电层。 然后，将图案化的迹线层电镀在第一开口中，并且第二抗蚀剂层被覆盖在具有图案化的迹线层的电路板上。 第二开口形成在第二抗蚀剂层中以暴露部分待用作电连接焊盘的迹线层。 此后，在第二开口中电镀金属凸块，并且用焊接掩模覆盖电路板的表面。 将薄化处理施加到焊料掩模以暴露金属凸块的顶表面。 之后，在从焊料掩模露出的金属凸块的表面上形成粘合剂层。

公开(公告)号：US20060237229A1

公开(公告)日：2006-10-26

申请号：US11410254

申请日：2006-04-25

Applicant: Hiroto Sugahara

Inventor： Hiroto Sugahara

IPC: H01L21/337

CPC classification number: H05K3/125 ,  H01L24/81 ,  H01L2224/10175 ,  H01L2224/81192 ,  H01L2924/12042 ,  H05K3/107 ,  H05K3/1258 ,  H05K3/321 ,  H05K3/4007 ,  H05K3/4069 ,  H05K2201/0367 ,  H05K2201/09036 ,  H05K2201/0949 ,  H05K2203/013 ,  Y10T29/49126 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A groove and a recess are formed on one surface of a base material, the recess being communicated with the groove and having a width and a length longer than a width of the groove. After that, liquid droplets are landed on the recess to charge a liquid into the groove communicated with the recess. Further, the liquid charged into the groove is solidified. Accordingly, the liquid can be charged into the groove having the narrow width, by merely landing the liquid droplets on the recess having a large areal size. Therefore, a fine pattern can be easily formed on the base material.

Abstract translation: 在基材的一个表面上形成有凹槽和凹槽，该凹槽与凹槽连通并且具有比凹槽的宽度更长的宽度和长度。 之后，液滴落在凹部上，以将液体充入与凹部连通的凹槽中。 此外，充入槽中的液体被固化。 因此，通过仅将液滴落在具有大面积尺寸的凹部上，液体可以被填充到具有窄宽度的凹槽中。 因此，能够容易地在基材上形成精细图案。

公开(公告)号：US20060234460A1

公开(公告)日：2006-10-19

申请号：US11106151

申请日：2005-04-13

Applicant: Lu-Chen Hwan

Inventor： Lu-Chen Hwan

IPC: H01L21/331 ,  H01L21/00

CPC classification number: H01L21/563 ,  G02F1/13452 ,  H01L2224/73203 ,  H01L2924/01079 ,  H05K1/118 ,  H05K3/244 ,  H05K3/305 ,  H05K3/325 ,  H05K3/361 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/10977

Abstract: A cable with conductive bumps is fabricated by forming a photoresist layer with multiple openings on a cable substrate, coating a conductive layer on the photoresist layer whereby the conductive layer in the openings forms the bumps at circuits on the cable substrate, and then removing the photoresist layer. When connecting the cable to a task object such as an LCD glass substrate or PCB, only a usual non-conductive paste is applied to join the cable and the task object, without use of expensive anisotropic-conductive paste or film.

Abstract translation: 具有导电凸块的电缆通过在电缆基底上形成具有多个开口的光致抗蚀剂层来制造，在光致抗蚀剂层上涂覆导电层，由此开口中的导电层在电缆基底上的电路处形成凸块，然后除去光致抗蚀剂 层。 当将电缆连接到诸如LCD玻璃基板或PCB的任务对象时，仅使用通常的不导电浆料来连接电缆和任务对象，而不使用昂贵的各向异性导电膏或膜。

公开(公告)号：US07109583B2

公开(公告)日：2006-09-19

申请号：US10841764

申请日：2004-05-06

Applicant: Edwin F. Johnson

Inventor： Edwin F. Johnson

IPC: H01L23/48

CPC classification number: H01L23/49816 ,  H01L23/49811 ,  H01L24/12 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/1403 ,  H01L2224/16 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01033 ,  H01L2924/0106 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15173 ,  H05K3/303 ,  H05K3/328 ,  H05K2201/0367 ,  H05K2201/09781 ,  H05K2201/10674 ,  H05K2201/2036 ,  H05K2203/0278 ,  Y02P70/613

Abstract: An electronic circuit can be produced by placing an electrically conductive compressible circuit bump on a circuit electrode of a mounting surface of first and second circuit devices, such as an integrated circuit and a base substrate. One or more auxiliary bumps can also be placed on one or both of the mounting surfaces of the circuit devices. During mounting, the first circuit device can be positioned over the second circuit device with the circuit bumps connecting circuit contacts on the two mounting surfaces. Pressure can be applied so that the circuit bumps and the auxiliary bumps are compressed between the chip and the base device sufficiently for adhering at least the circuit bumps to the circuit contacts.

Abstract translation: 可以通过在第一和第二电路装置（例如集成电路和基底）的安装表面的电路电极上放置导电的可压缩电路凸块来制造电子电路。 一个或多个辅助凸起也可以放置在电路装置的一个或两个安装表面上。 在安装期间，第一电路装置可以位于第二电路装置上方，电路凸块连接电路在两个安装表面上接触。 可以施加压力，使得电路凸块和辅助凸块在芯片和基底装置之间被充分压缩，以至少将电路凸块粘附到电路触点。