公开(公告)号：US20080272982A1

公开(公告)日：2008-11-06

申请号：US12174960

申请日：2008-07-17

Applicant: Gregory J. Dunn ,  Robert T. Croswell ,  George H. Kumpf ,  John A. Svigelj

Inventor： Gregory J. Dunn ,  Robert T. Croswell ,  George H. Kumpf ,  John A. Svigelj

IPC: H01Q15/24

CPC classification number: H01Q15/006 ,  H05K1/116 ,  H05K1/162 ,  H05K1/165 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2201/0715 ,  H05K2201/09509 ,  H05K2201/09609

Abstract: A high impedance surface (300) has a printed circuit board (302) with a first surface (314) and a second surface (316), and a continuous electrically conductive plate (319) disposed on the second surface (316) of the printed circuit board (302). A plurality of electrically conductive plates (318) is disposed on the first surface (314) of the printed circuit board (302), while a plurality of elements are also provided. Each element comprises at least one of (1) at least one multi-layer inductor (330, 331) electrically coupled between at least two of the electrically conductive plates (318) and embedded within the printed circuit board (302), and (2) at least one capacitor (320) electrically coupled between at least two of the electrically conductive plates (318). The capacitor (320) comprises at least one of (a) a dielectric material (328) disposed between adjacent electrically conductive plates, wherein the dielectric material (328) has a relative dielectric constant greater than 6, and (b) a mezzanine capacitor embedded within the printed circuit board (302).

Abstract translation: 高阻抗表面（300）具有带有第一表面（314）和第二表面（316）的印刷电路板（302）和设置在印刷的第二表面（316）上的连续导电板（319） 电路板（302）。 多个导电板（318）设置在印刷电路板（302）的第一表面（314）上，同时还提供多个元件。 每个元件包括（1）至少一个电耦合在至少两个导电板（318）之间并嵌入印刷电路板（302）内的多层电感器（330,331）中的至少一个，和（2 ）至少一个电耦合在至少两个导电板（318）之间的电容器（320）。 电容器（320）包括设置在相邻导电板之间的（a）介电材料（328）中的至少一个，其中介电材料（328）具有大于6的相对介电常数，以及（b）嵌入的夹层电容器 在印刷电路板（302）内。

公开(公告)号：US20080266810A1

公开(公告)日：2008-10-30

申请号：US11799057

申请日：2007-04-30

Applicant: Larry E. Tiedemann ,  Reinhold Henke ,  James P. Hentges ,  Dean R. McCluskey ,  Keith D. Ness ,  Robert A. Pape

Inventor： Larry E. Tiedemann ,  Reinhold Henke ,  James P. Hentges ,  Dean R. McCluskey ,  Keith D. Ness ,  Robert A. Pape

IPC: H05K7/20

CPC classification number: H05K7/20 ,  H05K1/0206 ,  H05K3/42 ,  H05K7/209 ,  H05K2201/09609 ,  H05K2201/09781 ,  H05K2201/10053

Abstract: A power switching device is provided that includes a housing, a printed circuit board disposed within the housing, and a plurality of electrical components mounted to the printed circuit board, including at least one relay. At least one pair of load terminals is connected to the printed circuit board on opposite sides of the relay, and a plurality of heat transfer elements are formed through and in the printed circuit board and are dispersed proximate the relay, around the load terminals, and extending to the peripheral portion.

Abstract translation: 提供一种电源开关装置，其包括壳体，设置在壳体内的印刷电路板，以及安装到印刷电路板的多个电气部件，包括至少一个继电器。 至少一对负载端子连接到继电器的相对侧上的印刷电路板，并且多个传热元件形成在印刷电路板中并且在印刷电路板中并且分散在靠近继电器的环绕负载端子处，并且 延伸到周边部分。

公开(公告)号：US07438581B1

公开(公告)日：2008-10-21

申请号：US11433099

申请日：2006-05-12

Applicant: Myoungsoo Jeon

Inventor： Myoungsoo Jeon

IPC: H01R4/50

CPC classification number: H01R12/523 ,  H01R12/57 ,  H01R12/714 ,  H05K1/0206 ,  H05K1/0231 ,  H05K1/141 ,  H05K3/3436 ,  H05K3/429 ,  H05K7/1069 ,  H05K7/1092 ,  H05K2201/049 ,  H05K2201/09609 ,  H05K2201/10333 ,  H05K2201/10704 ,  Y10S439/947

Abstract: A high speed socket includes an insulative housing and a printed circuit board body portion. The PCB body portion includes a PCB and surface mount contacts. Each surface mount contact has a first end portion for making contact with an integrated circuit held in the socket and a second end portion for surface mounting to a printed circuit board. The socket's printed circuit board includes AC grounded conductive columns (ACGCC) that extend from a first planar surface of the PCB to a second planar surface of the PCB. The printed circuit board also includes signal conductors. The signal conductors are shielded by the ACGCCs. In one aspect, the socket includes capacitors that are surface mounted to the socket's PCB. In another aspect, the surface mount contacts include self-adjusting solder tails that accommodate PCB warpage.

Abstract translation: 高速插座包括绝缘壳体和印刷电路板主体部分。 PCB主体部分包括PCB和表面安装触点。 每个表面安装触点具有用于与保持在插座中的集成电路接触的第一端部分和用于表面安装到印刷电路板的第二端部。 插座的印刷电路板包括从PCB的第一平面表面延伸到PCB的第二平面的AC接地导电柱（ACGCC）。 印刷电路板还包括信号导体。 信号导线被ACGCC屏蔽。 在一个方面，插座包括表面安装到插座的PCB的电容器。 在另一方面，表面安装触点包括适应PCB翘曲的自调整焊尾。

公开(公告)号：US07405947B1

公开(公告)日：2008-07-29

申请号：US11809595

申请日：2007-06-01

Applicant: Joel R. Goergen

Inventor： Joel R. Goergen

IPC: H01R12/16

CPC classification number: H05K1/0237 ,  H05K1/0219 ,  H05K1/0225 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/093 ,  H05K2201/09345 ,  H05K2201/09609 ,  H05K2201/09663

Abstract: For electrical backplanes and the like, a power plane adaptation to improve the propagation of high-speed signals through clearances in an embedded power plane is disclosed. In exemplary embodiments, the power plane is segmented in a high-speed connector region, such that a portion of the metal layer that forms the power plane is retained in the high-speed connector region—but isolated from the power-delivery portion of the power plane. The isolated portion is connected to digital ground, and clearances are formed therein where high-speed signaling throughholes will pass through the region. In some embodiments, various attainable advantages include better manufacturability, better matching and control of high-speed signaling throughhole impedance, and improved noise isolation. Other embodiments are described and claimed.

Abstract translation: 对于电气背板等，公开了一种用于改进高速信号通过嵌入式电源平面中的间隙的传播的电力平面适配。 在示例性实施例中，电力平面在高速连接器区域中被分段，使得形成电力平面的金属层的一部分保持在高速连接器区域中，但是与电力输送部分 电力飞机 隔离部分连接到数字地，并且在其中形成间隙，其中高速信令通孔将通过该区域。 在一些实施例中，各种可获得的优点包括更好的可制造性，更好地匹配和控制高速信号通孔阻抗以及改进的噪声隔离。 描述和要求保护其他实施例。

公开(公告)号：US07390742B2

公开(公告)日：2008-06-24

申请号：US11251594

申请日：2005-10-14

Applicant: Axel Brintzinger ,  Stefan Ruckmich ,  Octavio Trovarelli ,  Fritz Uhlendorf, legal representative ,  David Wallis

Inventor： Ingo Uhlendorf

IPC: H01L21/44

CPC classification number: H01L23/49827 ,  H01L21/4846 ,  H01L21/486 ,  H01L2924/0002 ,  H05K1/0287 ,  H05K1/0306 ,  H05K2201/09609 ,  Y10S438/976 ,  Y10T428/24273 ,  Y10T428/24322 ,  Y10T428/24331 ,  Y10T428/24917 ,  H01L2924/00

Abstract: The invention relates to a method for producing a rewiring printed circuit board with a substrate wafer having passage connections between a first and a second surface. One embodiment of the method comprises applying and patterning masking layers on the first and the second surfaces, thereby uncovering a first contact location on the first surface and a second contact location on the second surface; applying a protective layer to the second surface in order to protect the corresponding masking layer and the second contact location during subsequent method steps; applying a first conductor structure to the first surface, the first conductor structure on the first surface covering the first contact location; removing the protective layer on the second surface; and applying a second conductor structure to the second surface, the second conductor structure on the second surface covering the second contact location.

Abstract translation: 本发明涉及一种用于生产具有在第一和第二表面之间具有通道连接的基底晶片的再布线印刷电路板的方法。 该方法的一个实施例包括在第一和第二表面上施加和图案化掩模层，从而揭露第一表面上的第一接触位置和第二表面上的第二接触位置; 在第二表面施加保护层，以便在随后的方法步骤期间保护相应的掩蔽层和第二接触位置; 将第一导体结构施加到第一表面，第一表面上的第一导体结构覆盖第一接触位置; 去除第二表面上的保护层; 以及将第二导体结构施加到所述第二表面，所述第二表面上的所述第二导体结构覆盖所述第二接触位置。

公开(公告)号：US20080142257A1

公开(公告)日：2008-06-19

申请号：US11610082

申请日：2006-12-13

Applicant: Wiren D. Becker ,  Zhaoqing Chen ,  George Katopis

Inventor： Wiren D. Becker ,  Zhaoqing Chen ,  George Katopis

IPC: H05K1/11 ,  H05K1/00 ,  H05K1/03

CPC classification number: H05K1/0224 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2223/6622 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0219 ,  H05K1/0253 ,  H05K2201/09609 ,  H05K2201/09618 ,  H05K2201/09681 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  H01L2924/00

Abstract: Signal line conductors passing through vertical vias in an insulative substrate for supporting and interconnecting integrated circuit chips are provided with shielding conductors in adjacent vias that link respective power and ground planes. The shielding conductors' presence in positions around a signal via is made possible through the employment of power plane and ground plane conductive grids that are laid out in rhomboid patterns. The power plane and ground plane grids possess a left-right mirror relation to one another and are displaced to place the rhomboid's corners to avoid overlapping any of the grid lines.

Abstract translation: 通过垂直通孔的信号线导体在用于支撑和互连集成电路芯片的绝缘基板中设置有连接相应电源和接地层的相邻过孔中的屏蔽导体。 通过使用以菱形图案布置的电源平面和接地平面导电网格，​​可以使屏蔽导体存在于信号通孔周围的位置。 电力平面和地平面网格具有彼此的左右镜像关系，并被置换以放置菱形的角部，以避免重叠任何网格线。

公开(公告)号：US20070230149A1

公开(公告)日：2007-10-04

申请号：US11807027

申请日：2007-05-24

Applicant: Matthew Bibee

Inventor： Matthew Bibee

IPC: H01R12/16

CPC classification number: H05K1/0219 ,  H01R12/523 ,  H01R13/6471 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09609 ,  H05K2201/09618 ,  H05K2201/10189

Abstract: The embodiments of the present invention relate to an improved printed circuit board having additional rows of ground vias to reduce crosstalk in the board. A printed circuit board according to one embodiment of the present invention comprises a first row of vias and a second row of vias, each having a plurality of signal vias. The circuit board also comprises a plurality of rows of vias being coupled to a ground plane between the first row of signal vias and the second row of signal vias. According to one embodiment, the plurality of rows of vias being coupled to a ground plane comprise rows of vias having different sizes. Some of the vias are designed to receive a component, while others are generally smaller and designed to provide a return current path for the signal vias.

Abstract translation: 本发明的实施例涉及一种改进的印刷电路板，其具有附加的一排接地通孔，以减少电路板中的串扰。 根据本发明的一个实施例的印刷电路板包括第一行通孔和第二排通孔，每条通孔具有多个信号通路。 电路板还包括多个通孔的行，其耦合到第一行信号通孔和第二行信号通孔之间的接地平面。 根据一个实施例，耦合到接地平面的多排通孔包括具有不同尺寸的通孔列。 一些通孔被设计成接收组件，而其他通孔通常较小并被设计成为信号通路提供返回电流路径。

公开(公告)号：US07228623B2

公开(公告)日：2007-06-12

申请号：US10291876

申请日：2002-11-08

Applicant: Kevin C. Olson ,  Alan E. Wang

Inventor： Kevin C. Olson ,  Alan E. Wang

IPC: H01K3/10 ,  B05D1/36 ,  G03C5/00

CPC classification number: C09D5/4488 ,  H01L21/481 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/142 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/056 ,  H05K3/0023 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/388 ,  H05K3/426 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4608 ,  H05K2201/0179 ,  H05K2201/09554 ,  H05K2201/09609 ,  H05K2203/0582 ,  H05K2203/135 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49165 ,  H01L2924/00

Abstract: Processes for fabricating a multi-layer circuit assembly and a multi-layer circuit assembly fabricated by such processes are provided. The process includes (a) providing a substrate at least one area of which comprises a plurality of vias, these area(s) having a via density of 500 to 10,000 holes/square inch (75 to 1550 holes/square centimeter); (b) applying a dielectric coating onto all exposed surfaces of the substrate to form a conformal coating thereon; and (c) applying a layer of metal to all surfaces of the substrate. Additional processing steps such as circuitization may be included.

Abstract translation: 提供了用于制造多层电路组件的工艺和通过这些工艺制造的多层电路组件。 该方法包括（a）提供基底，其至少一个区域包括多个通孔，这些区域的通孔密度为500至10,000个孔/平方英寸（75至1550个孔/平方厘米）; （b）将介电涂层施加到所述基底的所有暴露表面上以在其上形成保形涂层; 和（c）在基片的所有表面上涂一层金属。 可以包括诸如电路化的附加处理步骤。

公开(公告)号：US07176578B2

公开(公告)日：2007-02-13

申请号：US11258763

申请日：2005-10-26

Applicant: Hans Evald Goran Martin ,  Klas Anders Hjort ,  Mikael Peter Erik Lindberg

Inventor： Hans Evald Goran Martin ,  Klas Anders Hjort ,  Mikael Peter Erik Lindberg

IPC: H01L23/48

CPC classification number: H05K3/0041 ,  G01K2211/00 ,  H01L2924/0002 ,  H05K1/115 ,  H05K3/002 ,  H05K2201/09609 ,  H05K2201/0979 ,  H05K2203/092 ,  H01L2924/00

Abstract: The present invention comprises a processed thin film substrate (10) and a method therefore, in order to produce a flexible printed circuit card, having a plurality of microvias going or passing through the thin film substrate and electrically connected along faced-away surfaces, in order to form an electric circuit. A first a number of real nano-tracks are filled with a first material (M1), having good electric properties, for the formation of a first number of, here denominated, first vias (V10, V30, V 50), that a second number of real nano-tracks are filled with a second material (M2), having good electric properties, for the formation of a second number of, here denominated, second vias (V20, V40, V60). The first material (M1) and the second material (M2) of said first and second vias (V10–V60) are chosen having mutually different thermoelectric properties. A material surface-applied to the thin film substrate, coated on both sides (10a, 10b) of the thin film substrate (10), is distributed and/or adapted in order to allow the electrical interconnection of first vias, allocated the first material (M1), with second vias, allocated the second material (M2), and that a first via (V10) included in a series connection and a last via (V60) included in the series connection are serially co-ordinated in order to form an electric thermocouple (100) or other circuit arrangement.

Abstract translation: 本发明包括一种处理过的薄膜基片（10）及其方法，以便制造出一种柔性印刷电路卡，其具有多个微孔进入或通过薄膜基片并沿着相对表面电连接， 以形成电路。 第一个真正的纳米轨道填充有具有良好电性能的第一材料（M1），用于形成第一数量的这里计量的第一通孔（V 10，V 30，V 50）， 第二数量的真实纳米轨道填充有具有良好电性能的第二材料（M 2），用于形成第二数量的这里计数的第二通孔（V 20，V 40，V 60）。 选择所述第一和第二通孔（V 10 -V 60）的第一材料（M 1）和第二材料（M 2）具有相互不同的热电性质。 涂布在薄膜基板（10a，10b）的两侧（10a，10b）上的表面施加到薄膜基板上的材料被分布和/或适配，以便允许第一通孔的电互连， 具有第二通孔的第一材料（M 1）分配第二材料（M 2），并且串联连接中包括的第一通孔（V 10）和串联连接中包括的最后通孔（V 60）是串联的 为了形成电热电偶（100）或其他电路布置。

公开(公告)号：US07122881B2

公开(公告)日：2006-10-17

申请号：US10807195

申请日：2004-03-24

Applicant: Sotaro Tsukamoto ,  Satoru Kuromiya ,  Nobuhiro Hanai ,  Masato Hayashida

Inventor： Sotaro Tsukamoto ,  Satoru Kuromiya ,  Nobuhiro Hanai ,  Masato Hayashida

IPC: H01L23/552 ,  H01L39/00 ,  H01L29/00

CPC classification number: H01L23/552 ,  H01L23/49805 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/16152 ,  H01L2924/19105 ,  H01L2924/3025 ,  H05K1/0218 ,  H05K1/185 ,  H05K2201/09609 ,  H01L2224/05599

Abstract: A wiring board houses a bare radio-frequency IC. Shield wiring films are provided above and below the IC. A plurality of shield interlayer-connection conductor films, i.e., shield via-holes, is provided so as to surround the IC. The shield wiring films and the shield interlayer-connection conductor films define a shield cage, which can electrostatically shield the IC. Thus, there is no need to attach a shield cap.

Abstract translation: 接线板上装有裸露的射频IC。 在IC上方和下方提供屏蔽布线膜。 提供多个屏蔽层间连接导体膜，即屏蔽通孔，以便围绕IC。 屏蔽布线膜和屏蔽层间连接导体膜限定了可以静电屏蔽IC的屏蔽笼。 因此，不需要附加屏蔽盖。