公开(公告)号：US07932470B2

公开(公告)日：2011-04-26

申请号：US11850325

申请日：2007-09-05

Applicant: Hiroaki Kurihara

Inventor： Hiroaki Kurihara

IPC: H05K1/00

CPC classification number: H05K1/147 ,  H01L23/49572 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/4985 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01067 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K1/142 ,  H05K2201/0784 ,  H05K2201/098 ,  H05K2201/10681 ,  H01L2224/0401

Abstract: A printed wiring board group includes a plurality of printed wiring boards wherein a difference (ΔΩ−AB) between an average electric resistance (A-ave.) of wires formed in one printed wiring board (A) and an average electric resistance (B-ave.) of wires formed in a printed wiring board (B) adjacent to the printed wiring board (A) is within a range of ±5% of an average electric resistance (AB-ave.) of the wires of the printed wiring boards (A) and (B); and a difference (ΔΩ−ab) between an electric resistance (a-3) of an outermost wire of the printed wiring board (A) and an electric resistance (b-3) of an outermost wire of the printed wiring board (B) is within a range of ±11.05%, preferably within a range of ±6.12%, and is particularly preferably within a range of ±6.00% of the average electric resistance (AB-ave.) of the printed wiring boards (A) and (B).

Abstract translation: 印刷电路板组包括多个印刷电路板，其中形成在一个印刷电路板（A）中的电线的平均电阻（A-ave）与平均电阻之间的差异（＆Dgr;＆Omega; -AB） 在与印刷电路板（A）相邻的印刷电路板（B）中形成的电线（B-ave。）的线的平均电阻（AB-ave。）为±5％ 印刷电路板（A）和（B）; 以及印刷电路板（A）的最外层导线的电阻（a-3）与印刷线路板（A）的最外层导线的电阻（b-3）之间的差异（＆Dgr;＆amp; （B）在±11.05％的范围内，优选在±6.12％的范围内，特别优选在印刷电路板（A）的平均电阻（AB-ave。）的±6.00％的范围内 ）和（B）。

公开(公告)号：US20110083881A1

公开(公告)日：2011-04-14

申请号：US12969478

申请日：2010-12-15

Applicant: Vinh T. Nguyen ,  Claude A.S. Hamrick

Inventor： Vinh T. Nguyen ,  Claude A.S. Hamrick

IPC: H05K1/02 ,  H05K3/00

CPC classification number: H05K3/1258 ,  H05K3/108 ,  H05K3/125 ,  H05K3/243 ,  H05K3/4611 ,  H05K3/4623 ,  H05K2201/09318 ,  H05K2201/09327 ,  H05K2201/09536 ,  H05K2201/098 ,  H05K2203/013 ,  H05K2203/0568 ,  Y10T29/49002 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A multilayer circuit device having electrically isolated tightly spaced electrical current carrying traces and including a first nonconductive substrate having a first conductive material affixed to a first side thereof to form a first ground plane, a plurality of elongated first conductive traces formed on a second side of the first non-conductive substrate and having transverse widths of 50 microns or less and rising above the upper surface of the first substrate to a height equal to or greater than the widths thereof such that a transverse cross section of the first conductive traces has a height-to-width ratio equal to or exceeding 1, adjacent ones of the first traces being separated from each other by first elongated spaces, the first conductive traces being variously useful as ground lines, signal lines and/or power lines.

Abstract translation: 一种具有电隔离紧密间隔的电流载流迹线并包括第一非导电基底的多层电路器件，所述第一非导电基底具有固定到其第一侧的第一导电材料以形成第一接地平面;多个细长的第一导电迹线，形成在第二侧 第一非导电衬底并且具有50微米或更小的横向宽度并且在第一衬底的上表面上方升高到等于或大于其宽度的高度，使得第一导电迹线的横截面具有高度 宽度比等于或超过1，相邻的第一迹线通过第一细长空间彼此分开，第一导电迹线在各种不同地用作接地线，信号线和/或电力线。

公开(公告)号：US20110027942A1

公开(公告)日：2011-02-03

申请号：US12903482

申请日：2010-10-13

Applicant: Horst Theuss ,  Adolf Koller

Inventor： Horst Theuss ,  Adolf Koller

IPC: H01L21/768

CPC classification number: H05K3/3442 ,  H01L21/78 ,  H01L24/03 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L29/0657 ,  H01L2224/02371 ,  H01L2224/035 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05556 ,  H01L2224/05568 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/29035 ,  H01L2224/29111 ,  H01L2224/32105 ,  H01L2224/83801 ,  H01L2224/83851 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/0106 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10156 ,  H05K2201/098 ,  H05K2201/10727 ,  Y02P70/613 ,  H01L2224/05552

Abstract: A semiconductor package is disclosed. One embodiment provides a semiconductor package singulated from a wafer includes a chip defining an active surface, a back side opposite the active surface, and peripheral sides extending between the active surface and the back side; a contact pad disposed on the active surface; and a metallization layer extending from the contact pad onto a portion of the peripheral sides of the chip.

Abstract translation: 公开了半导体封装。 一个实施例提供了从晶片单个化的半导体封装，其包括限定有源表面的芯片，与有源表面相对的后侧，以及在有源表面和背面之间延伸的周边; 设置在所述活动表面上的接触垫; 以及从接触垫延伸到芯片周边的一部分上的金属化层。

公开(公告)号：US07874065B2

公开(公告)日：2011-01-25

申请号：US12263416

申请日：2008-10-31

Applicant: Vinh T. Nguyen ,  Claude A. S. Hamrick

Inventor： Vinh T. Nguyen ,  Claude A. S. Hamrick

IPC: H05K3/36

CPC classification number: H05K3/1258 ,  H05K3/108 ,  H05K3/125 ,  H05K3/243 ,  H05K3/4611 ,  H05K3/4623 ,  H05K2201/09318 ,  H05K2201/09327 ,  H05K2201/09536 ,  H05K2201/098 ,  H05K2203/013 ,  H05K2203/0568 ,  Y10T29/49002 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A process for making a multi-layered circuit board having electrical current traces includes providing a substrate having a 1st layer of conductive material to form a ground plane, plurality of metallic 1st traces on a 2nd side of the substrate having widths of approximately 25 microns or less, developing 1st ribs of photoresist forming 1st walls rising above upper surface of an adjacent seed layer trace, depositing 1st conductive signal traces having a thickness exceeding 25 microns into channels and over seed layer traces and stripping the ribs to leave 1st conductive traces having a height-to-transverse ratio exceeding 1.

Abstract translation: 用于制造具有电流迹线的多层电路板的方法包括提供具有第一层导电材料以形成接地平面的衬底，在衬底的第二面上的多个金属第一迹线具有约25微米的宽度或 在相邻的种子层迹线的上表面上方形成第一壁的第一肋形成第一肋，将厚度超过25微米的第一导电信号迹线沉积到通道中并且超过种子层迹线并剥离肋，以留下第一导电迹线， 高度与横向之比超过1。

公开(公告)号：US07830022B2

公开(公告)日：2010-11-09

申请号：US11876241

申请日：2007-10-22

Applicant: Horst Theuss ,  Adolf Koller

Inventor： Horst Theuss ,  Adolf Koller

IPC: H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC classification number: H05K3/3442 ,  H01L21/78 ,  H01L24/03 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L29/0657 ,  H01L2224/02371 ,  H01L2224/035 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05556 ,  H01L2224/05568 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/29035 ,  H01L2224/29111 ,  H01L2224/32105 ,  H01L2224/83801 ,  H01L2224/83851 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/0106 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10156 ,  H05K2201/098 ,  H05K2201/10727 ,  Y02P70/613 ,  H01L2224/05552

Abstract: A semiconductor package is disclosed. One embodiment provides a semiconductor package singulated from a wafer includes a chip defining an active surface, a back side opposite the active surface, and peripheral sides extending between the active surface and the back side; a contact pad disposed on the active surface; and a metallization layer extending from the contact pad onto a portion of the peripheral sides of the chip.

Abstract translation: 公开了半导体封装。 一个实施例提供了从晶片单个化的半导体封装，其包括限定有源表面的芯片，与有源表面相对的后侧，以及在有源表面和背面之间延伸的周边; 设置在所述活动表面上的接触垫; 以及从接触垫延伸到芯片周边的一部分上的金属化层。

公开(公告)号：US07679004B2

公开(公告)日：2010-03-16

申请号：US10598524

申请日：2005-03-02

Applicant: Katsuya Fukase ,  Toyoaki Sakai ,  Munetoshi Irisawa ,  Toyokazu Komuro ,  Yasuo Kaneda ,  Masanori Natsuka ,  Wakana Aizawa

Inventor： Katsuya Fukase ,  Toyoaki Sakai ,  Munetoshi Irisawa ,  Toyokazu Komuro ,  Yasuo Kaneda ,  Masanori Natsuka ,  Wakana Aizawa

IPC: H01R12/04 ,  H05K1/00

CPC classification number: H05K3/064 ,  H05K1/116 ,  H05K3/0094 ,  H05K3/061 ,  H05K3/065 ,  H05K3/108 ,  H05K3/421 ,  H05K3/427 ,  H05K2201/09381 ,  H05K2201/09563 ,  H05K2201/09581 ,  H05K2201/098 ,  H05K2203/0517 ,  H05K2203/0577 ,  H05K2203/0582 ,  H05K2203/1184 ,  H05K2203/1394

Abstract: As means for solving a problem of a positional shift of a land and a hole which is caused by an alignment in the formation of an etching resist layer and a plated resist layer in a method of manufacturing a circuit board, there are provided a method of manufacturing a circuit board including the steps of forming a first resin layer on a surface of an insulating substrate having a conductive layer on the surface and an internal wall of a through hole or/and a non-through hole, forming a second resin layer which is insoluble or slightly soluble in a developing solution for the first resin layer on the first resin layer provided on the surface conductive layer, and removing the first resin layer provided over the hole with the developing solution for the first resin layer, and a method of manufacturing a circuit board including the step of uniformly charging a surface of the first resin layer to induce a potential difference to the first resin layer provided over the hole and the first resin layer provided on the surface conductive layer before forming the second resin layer. Moreover, there is provided a circuit board having a hole with a small positional shift and high precision.

Abstract translation: 作为在电路基板的制造方法中解决在形成抗蚀剂层和电镀抗蚀剂层时的取向引起的焊盘和孔的位置偏移的问题的方法，提供了一种方法， 制造电路板，包括以下步骤：在表面上具有导电层的绝缘基板的表面上形成第一树脂层和通孔或/或非通孔的内壁，形成第二树脂层，所述第二树脂层 在设置在表面导电层上的第一树脂层上的第一树脂层的显影液中不溶或微溶，用第一树脂层的显影液除去设在孔上的第一树脂层， 制造电路板，包括对第一树脂层的表面均匀充电以对设置在孔上的第一树脂层引起电位差的步骤， 在形成第二树脂层之前，在表面导电层上设置阴极层。 此外，提供一种电路板，其具有位置偏移小且精度高的孔。

公开(公告)号：US20090242256A1

公开(公告)日：2009-10-01

申请号：US12410685

申请日：2009-03-25

Applicant: Hitoshi Saita ,  Kenji Horino ,  Yasunobu Oikawa ,  Shinichiro Kakei

Inventor： Hitoshi Saita ,  Kenji Horino ,  Yasunobu Oikawa ,  Shinichiro Kakei

IPC: H05K1/18

CPC classification number: H05K1/162 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2201/098

Abstract: In a dielectric element, the angle θ made by either the top face or the bottom face and the side faces is either 0°

Abstract translation: 在电介质元件中，由顶面或底面和侧面形成的角度θ为0°<89°，或91°<180°，并且为89°以外的角度 <=θ<= 91°。 通过这种方式，介电元件的侧面与玻璃环氧树脂基板和绝缘材料的接触面积增加，与树脂基板的粘附性提高，并且当埋在两个树脂之间时，可以提高强度和可靠性 底物。

公开(公告)号：US07547974B2

公开(公告)日：2009-06-16

申请号：US11640262

申请日：2006-12-18

Applicant: Wen-Jeng Fan

Inventor： Wen-Jeng Fan

IPC: H01L23/48 ,  H05K1/00 ,  H05K7/00

CPC classification number: H05K1/0271 ,  H01L23/498 ,  H01L2924/0002 ,  H05K1/0265 ,  H05K3/28 ,  H05K2201/09672 ,  H05K2201/098 ,  H05K2203/0733 ,  H01L2924/00

Abstract: A wiring substrate with tensile-strength enhanced traces primarily comprises a core layer, a plurality of connecting pads, a plurality of traces, and a solder resist where the connecting pads and the traces are disposed on a top of the core layer. The solder resist is formed over the top of the core layer to cover the traces with the connecting pads partially or completely exposed. Furthermore, the traces have I-shaped cross sections to enhance the tensile strength of the traces.

Abstract translation: 具有拉伸强度增强迹线的布线基板主要包括芯层，多个连接焊盘，多个迹线和阻焊层，其中连接焊盘和迹线设置在芯层的顶部。 阻焊层形成在芯层的顶部上，以覆盖具有部分或完全暴露的连接焊盘的迹线。 此外，迹线具有I形横截面以增强迹线的拉伸强度。

公开(公告)号：US07521811B2

公开(公告)日：2009-04-21

申请号：US11044836

申请日：2005-01-28

Applicant: Yung Teng Pan ,  Chia Hung Chen

Inventor： Yung Teng Pan ,  Chia Hung Chen

IPC: H01L29/40 ,  H01L21/44

CPC classification number: H01L23/498 ,  H01L21/4846 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/14 ,  H01L2924/15311 ,  H05K3/062 ,  H05K3/108 ,  H05K3/244 ,  H05K3/3452 ,  H05K2201/098 ,  H05K2201/0989 ,  H05K2201/099 ,  H01L2924/00014

Abstract: A substrate for packaging a semiconductor chip includes a dielectric layer, a plurality of conductive circuits and bonding pads formed on the dielectric layer, a metal thin deposition layer formed on the conductive circuits and the bonding pads, and a solder mask formed on the dielectric layer and the conductive circuits. The first ends of the bonding pads extend from the conductive circuits. The metal thin deposition layer has at least a portion to protrude out of the conductive circuits and the bonding pads such that the protruding portion of the metal thin position layer is not supported by the conductive circuits or the bonding pads. The bonding pads are exposed form the solder mask except that the second end of each bonding pad is covered by the solder by the solder mask in the manner that the protruding portion of the metal thin deposition layer is embedded in the solder mask.

Abstract translation: 用于封装半导体芯片的基板包括电介质层，形成在电介质层上的多个导电电路和接合焊盘，形成在导电电路和接合焊盘上的金属薄沉积层，以及形成在电介质层上的焊料掩模 和导电电路。 接合焊盘的第一端从导电电路延伸。 金属薄沉积层至少有一部分从导电电路和接合焊盘突出出来，使得金属薄层位置层的突出部分不被导电电路或接合焊盘支撑。 接合焊盘从焊料掩模露出，除了金属薄沉积层的突出部分嵌入焊接掩模中的方式之外，通过焊料掩模将每个接合焊盘的第二端覆盖焊料。

公开(公告)号：US07487587B2

公开(公告)日：2009-02-10

申请号：US11387446

申请日：2006-03-22

Applicant: Jan Vanfleteren ,  Dominique Brosteaux ,  Fabrice Axisa

Inventor： Jan Vanfleteren ,  Dominique Brosteaux ,  Fabrice Axisa

IPC: H05K3/02 ,  H01R43/00

CPC classification number: H01L25/50 ,  H01L25/0655 ,  H01L2924/0002 ,  H05K1/0393 ,  H05K3/205 ,  H05K2201/0133 ,  H05K2201/098 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49158 ,  H01L2924/00

Abstract: Methods of producing a composite substrate and devices made by the methods are disclosed. One of the methods comprises providing a flexible sacrificial layer, producing one or more patterned conducting layers on the flexible sacrificial layer, bending the sacrificial layer into a predetermined shape, providing a stretchable and/or flexible material on top of and in between features of the one or more patterned layers.

Abstract translation: 公开了制造复合基板的方法和由该方法制成的装置。 其中一种方法包括提供柔性牺牲层，在柔性牺牲层上产生一个或多个图案化的导电层，将牺牲层弯曲成预定的形状，提供可拉伸和/或柔性材料， 一个或多个图案层。