公开(公告)号：US20110232086A1

公开(公告)日：2011-09-29

申请号：US13156715

申请日：2011-06-09

Applicant: Youhong Wu

Inventor： Youhong Wu

IPC: H05K3/46

CPC classification number: H05K1/115 ,  H05K3/4602 ,  H05K2201/0347 ,  H05K2201/0352 ,  H05K2201/09454 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09627 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method of manufacturing a multi-layer printed wiring board including forming a core substrate, forming a first interlayer insulation layer over the core substrate, forming a first filled via in the first interlayer insulation layer, the first filled via having a bottom portion having a first diameter, forming a second interlayer insulation layer over the first interlayer insulation layer, and forming a second filled via in the second interlayer insulation layer, the second filled via having a bottom portion having a second diameter smaller than the first diameter.

Abstract translation: 一种制造多层印刷布线板的方法，包括形成芯基板，在芯基板上形成第一层间绝缘层，在第一层间绝缘层中形成第一填充通孔，第一填充通孔具有底部， 在所述第一层间绝缘层上形成第二层间绝缘层，在所述第二层间绝缘层中形成第二填充通孔，所述第二填充通孔具有第二直径小于所述第一直径的第二直径。

公开(公告)号：US20110203937A1

公开(公告)日：2011-08-25

申请号：US13126914

申请日：2009-10-28

Applicant: Jagit Sidhu

Inventor： Jagit Sidhu

IPC: C25D5/08 ,  C25D17/10

CPC classification number: C25D5/04 ,  B33Y10/00 ,  B33Y30/00 ,  C25D5/02 ,  H05K3/1241 ,  H05K3/188 ,  H05K3/241 ,  H05K3/246 ,  H05K2201/0347 ,  H05K2203/0195 ,  H05K2203/092 ,  H05K2203/101

Abstract: A method is disclosed which includes applying a surface treatment to a substrate to form a patterned area having at least some electrical conductivity; electroplating onto the patterned area with a tool having a first electrode and a source for in situ supply of electrolyte, by providing an anode current to the first electrode, causing the patterned area at least in the vicinity of the tool to function as a cathode, and passing electrolyte between the patterned area and the first electrode, thereby to deposit conductive material onto the patterned area.

Abstract translation: 公开了一种方法，其包括对基板施加表面处理以形成具有至少一些导电性的图案化区域; 通过向第一电极提供阳极电流，使具有第一电极和用于原位供应电解质的源的工具电镀到图案化区域上，使得至少在工具附近的图案化区域用作阴极， 并且在图案化区域和第一电极之间通过电解质，从而将导电材料沉积到图案化区域上。

公开(公告)号：US20110094889A1

公开(公告)日：2011-04-28

申请号：US12841529

申请日：2010-07-22

Applicant: Dong-Youn SHIN ,  Inyoung KIM

Inventor： Dong-Youn SHIN ,  Inyoung KIM

IPC: C25D5/02

CPC classification number: H05K3/1258 ,  C09D5/38 ,  C09D11/101 ,  H01L31/022425 ,  H05K3/105 ,  H05K3/246 ,  H05K2201/0347 ,  H05K2203/121 ,  Y02E10/50

Abstract: Provided is a method for forming a highly conductive micropattern, including: depositing a polymer material on a substrate; removing a portion of the polymer material to form a mask template having a dent through which a portion of the substrate is exposed to the exterior; depositing conductive ink to the top of the mask; heat treating the conductive ink in order to extract metal nanoclusters from a metallic compound dissolved in the conductive ink, wherein the portion coated with the polymer material is allowed to form an insulating pattern having electrically insulating property, while the conductive ink in the dent forms a conductive pattern having electroconductive property by the fusion of the metal nanoclusters extracted from the conductive ink; and plating a metallic material on the conductive pattern.

Abstract translation: 提供一种形成高导电性微图案的方法，包括：将聚合物材料沉积在基底上; 去除一部分聚合物材料以形成具有凹陷的掩模模板，通过该凹陷将基底的一部分暴露于外部; 将导电油墨沉积到掩模的顶部; 热处理导电油墨以从溶解在导电油墨中的金属化合物提取金属纳米团簇，其中涂覆有聚合物材料的部分被允许形成具有电绝缘性能的绝缘图案，而凹陷中的导电油墨形成 导电图案具有通过从导电油墨提取的金属纳米团簇的融合而具有导电性; 并在导电图案上镀金属材料。

公开(公告)号：US07898811B2

公开(公告)日：2011-03-01

申请号：US12054618

申请日：2008-03-25

Applicant: Kurt J. Storey

Inventor： Kurt J. Storey

IPC: H05K7/20

CPC classification number: H01R13/7175 ,  F21K9/00 ,  F21V29/70 ,  G09F9/33 ,  H05K1/0206 ,  H05K3/0061 ,  H05K3/4069 ,  H05K2201/0347 ,  H05K2201/0959 ,  H05K2201/10106 ,  Y10T29/49139

Abstract: A light emitting diode (LED) lighting assembly includes a printed circuit board that includes a dielectric layer sandwiched between first conductive layers. The printed circuit board includes vias extending there through, with thermally conductive plugs in the vias. A second conductive layer is on each first conductive layer and on the thermally conductive plugs. The thermally conductive plugs are enclosed by the second conductive layers. LEDs are coupled to the printed circuit board, with each LED being mounted over at least one thermally conductive plug to dissipate heat therefrom.

Abstract translation: 发光二极管（LED）照明组件包括印刷电路板，其包括夹在第一导电层之间的电介质层。 印刷电路板包括在其中延伸的通孔，通孔中具有导热插头。 第二导电层位于每个第一导电层上和导热塞上。 导热塞被第二导电层包围。 LED耦合到印刷电路板，每个LED安装在至少一个导热插塞上以从其中散发热量。

公开(公告)号：US20100243601A1

公开(公告)日：2010-09-30

申请号：US12659893

申请日：2010-03-24

Applicant: Hiroyuki Uematsu ,  Kenichi Kawabata ,  Kenji Nagase

Inventor： Hiroyuki Uematsu ,  Kenichi Kawabata ,  Kenji Nagase

IPC: C23F1/00 ,  H01B13/00

CPC classification number: H05K3/427 ,  H05K3/002 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/0041 ,  H05K3/0044 ,  H05K3/061 ,  H05K3/064 ,  H05K3/382 ,  H05K3/389 ,  H05K3/421 ,  H05K3/4652 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/0358 ,  H05K2201/0394 ,  H05K2203/025 ,  H05K2203/0353 ,  H05K2203/054 ,  H05K2203/0585 ,  H05K2203/0733

Abstract: Provided is a method for manufacturing a multilayer wiring board, whereby even if the multilayer wiring board suffers warping or irregularities, thin-film patterns with great uniformity that are to be used as a mask for forming a wiring layer can be obtained in a simple way. A primer-coated metal foil 20 composed of a primer resin layer 21 and a metal layer 22 is placed on a surface of a double-face CCL 10, which is prepared by applying metal layers 12 and 13 onto the surfaces of a support base 11, and the primer-coated metal foil 20 and the double-face CCL 10 are bonded and the primer resin layer 21 is cured. A via Vb is thereafter formed from the metal layer 22 side, and a metal-plate layer 30 is formed on the resulting metal layer 22. After that, the etched down metal-plate layer 30 and the metal layer 22 are patterned, and using the patterned layers as a mask, the primer resin layer 21 is patterned. Using the patterned primer resin layer 21 as a mask, the metal layer 12 of the double-face CCL 10 and the metal-plate layer 30 are patterned to form a wiring pattern.

Abstract translation: 提供一种多层布线板的制造方法，即使多层布线板发生翘曲或不均匀，也可以以简单的方式获得用作形成布线层的掩模的具有均匀性的薄膜图案 。 将由底漆树脂层21和金属层22构成的底漆涂布金属箔20放置在双面CCL 10的表面上，该双面CCL 10通过将金属层12和13施加到支撑基底11的表面上而制备 并且底漆涂覆的金属箔20和双面CCL 10被粘合，底漆树脂层21固化。 之后，从金属层22侧形成通孔Vb，在所得到的金属层22上形成金属板层30.之后，对蚀刻后的金属板层30和金属层22进行图案化，使用 作为掩模的图案化层，对底漆树脂层21进行图案化。 使用图案化底漆树脂层21作为掩模，将双面CCL 10的金属层12和金属板层30图案化以形成布线图案。

公开(公告)号：US20100243149A1

公开(公告)日：2010-09-30

申请号：US12738794

申请日：2008-10-03

Applicant: Shigeo Hashimoto ,  Teruyuki Hotta ,  Takahiro Ishizaki

Inventor： Shigeo Hashimoto ,  Teruyuki Hotta ,  Takahiro Ishizaki

IPC: B32B37/00 ,  B29C65/00

CPC classification number: H05K3/246 ,  H05K1/0265 ,  H05K3/0023 ,  H05K3/184 ,  H05K3/28 ,  H05K2201/0347 ,  H05K2201/0376 ,  H05K2203/072 ,  Y10T156/1082

Abstract: A method for forming a circuit pattern is disclosed. A circuit pattern that forms an electrically conductive layer (2L) is formed on an insulating resin (11) that forms a first insulating layer (1L). An insulating resin (13) that forms a second insulating layer (3L) is laminated on the insulating resin (11) on which the circuit pattern has been formed. A trench (14) is formed in the laminated insulating resin (13) to expose the circuit pattern. An electroless plating metal (15) is buried by electroless plating in the trench (14) formed.

Abstract translation: 公开了一种形成电路图案的方法。 在形成第一绝缘层（1L）的绝缘树脂（11）上形成形成导电层（2L）的电路图案。 在形成有电路图案的绝缘树脂（11）上层压形成第二绝缘层（3L）的绝缘树脂（13）。 在叠层绝缘树脂（13）中形成沟槽（14）以露出电路图案。 化学镀金属（15）通过化学镀被埋在形成的沟槽（14）中。

公开(公告)号：US20100236065A1

公开(公告)日：2010-09-23

申请号：US12791701

申请日：2010-06-01

Applicant: Garo MIYAMOTO

Inventor： Garo MIYAMOTO

IPC: H05K3/10

CPC classification number: H05K1/167 ,  H05K3/243 ,  H05K3/4069 ,  H05K2201/0323 ,  H05K2201/0347 ,  H05K2201/0394 ,  H05K2201/0969 ,  H05K2203/107 ,  H05K2203/171 ,  Y10T29/49082 ,  Y10T29/49099 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155

Abstract: There is provided a method of producing a printed circuit board incorporating a resistance element capable of adjusting resistance after the resistance element has been formed and assuring a high accurate resistance. A method of producing a printed circuit board incorporating a resistance element using carbon paste includes the steps of: forming through holes 5, 6, 25 and 26 or a bottomed hole in a double-sided copper clad laminate; applying noble metal plating into the through hole or the bottomed hole; filling the through hole or the bottomed hole with carbon paste; subjecting the carbon paste with which the thorough hole or the bottomed hole is filled to noble metal plating, conducting treatment and plating to form a conductive layer; forming an opening 18 in the conductive layer on the end of the through hole filled with the carbon paste; and performing trimming through the opening to adjust the resistance of the resistor formed by the carbon paste.

Abstract translation: 提供了一种制造印刷电路板的方法，该印刷电路板包括能够在电阻元件形成之后能够调节电阻的电阻元件并且确保高精度的电阻。 制造使用碳膏包含电阻元件的印刷电路板的方法包括以下步骤：在双面铜箔层压板中形成通孔5,62,26或有底孔; 将贵金属电镀施加到通孔或有底孔中; 用碳浆填充通孔或有孔孔; 对填充有通孔或有底孔的碳糊进行贵金属电镀，进行处理和电镀以形成导电层; 在填充有碳糊的通孔的端部的导电层中形成开口18; 并通过开口进行修整以调节由碳浆形成的电阻器的电阻。

公开(公告)号：US07795542B2

公开(公告)日：2010-09-14

申请号：US11333228

申请日：2006-01-18

Applicant: Yogo Kawasaki ,  Hiroaki Satake ,  Yutaka Iwata ,  Tetsuya Tanabe

Inventor： Yogo Kawasaki ,  Hiroaki Satake ,  Yutaka Iwata ,  Tetsuya Tanabe

IPC: H01R12/04 ,  H05K1/11

CPC classification number: H05K1/113 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K3/0055 ,  H05K3/0094 ,  H05K3/3457 ,  H05K3/381 ,  H05K3/382 ,  H05K3/426 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/0209 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/0796 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/05599

Abstract: Through holes 36 are formed to penetrate a core substrate 30 and lower interlayer resin insulating layers 50, and via holes 66 are formed right on the through holes 36, respectively. Due to this, the through holes 36 and the via holes 66 are arranged linearly, thereby making it possible to shorten wiring length and to accelerate signal transmission speed. Also, since the through holes 36 and the via holes 66 to be connected to solder bumps 76 (conductive connection pins 78), respectively, are directly connected to one another, excellent reliability in connection is ensured.

Abstract translation: 通孔36形成为穿透芯基板30和下层层间树脂绝缘层50，并且通孔66分别形成在通孔36上。 由此，通孔36和通路孔66线性配置，能够缩短布线长度，加速信号传输速度。 此外，由于分别连接到焊料凸块76（导电连接销78）的通孔36和通孔66彼此直接连接，所以确保了良好的连接可靠性。

公开(公告)号：US20100170626A1

公开(公告)日：2010-07-08

申请号：US12601669

申请日：2008-05-20

Applicant: Rene Lochtman ,  Jürgen Kaczun ,  Norbert Wagner ,  Jürgen Pfister ,  Dieter Hentschel

Inventor： Rene Lochtman ,  Jürgen Kaczun ,  Norbert Wagner ,  Jürgen Pfister ,  Dieter Hentschel

IPC: B32B38/08 ,  C25D5/34 ,  B05D3/02 ,  B05D3/10 ,  B05D3/04 ,  B32B37/02 ,  B32B38/10 ,  B32B38/16 ,  C25D5/48 ,  C25D5/54

CPC classification number: B05D1/286 ,  B05D1/00 ,  B05D3/101 ,  B05D5/12 ,  B05D7/577 ,  B05D2350/33 ,  B32B38/0012 ,  B32B38/10 ,  B32B2037/243 ,  B32B2038/0092 ,  B32B2310/0843 ,  H05K1/095 ,  H05K3/025 ,  H05K2201/0347 ,  H05K2203/0716 ,  H05K2203/072 ,  H05K2203/0723 ,  Y10T156/10

Abstract: The invention relates to a method for producing polymer-coated metal foils, comprising the following steps: (a) applying a base layer (7) onto a support foil (3), with a dispersion (5) which comprises electrolessly and/or electrolytically coatable particles in a matrix material, (b) at least partially drying and/or at least partially curing the matrix material, (c) forming a metal layer (19) on the base layer (7) by electroless and/or electrolytic coating of the base layer (7) comprising the electrolessly or electrolytically coatable particles, (d) applying a polymer (23) to the metal layer (19). Furthermore, the invention relates to a use of the polymer-coated metal foil for the production of printed circuit boards.

Abstract translation: 本发明涉及一种生产聚合物涂覆的金属箔的方法，包括以下步骤：（a）将基底层（7）施加到载体箔（3）上，其中分散体（5）包括无电解和/或电解 （b）至少部分干燥和/或至少部分固化基质材料，（c）通过无电解和/或电解涂覆在基底层（7）上形成金属层（19）， 所述基层（7）包括无电解或可电解涂覆的颗粒，（d）将聚合物（23）施加到所述金属层（19）。 此外，本发明涉及聚合物涂覆的金属箔用于制造印刷电路板的用途。

公开(公告)号：US20100170088A1

公开(公告)日：2010-07-08

申请号：US12725460

申请日：2010-03-17

Applicant: Chien-Wei Chang ,  Ting-Hao Lin ,  Jen-Fang Chang ,  Yu-Te Lu ,  Chia-Chi Lo

Inventor： Chien-Wei Chang ,  Ting-Hao Lin ,  Jen-Fang Chang ,  Yu-Te Lu ,  Chia-Chi Lo

IPC: H05K3/10

CPC classification number: H05K3/4602 ,  H05K3/108 ,  H05K3/427 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/0959 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49165

Abstract: Structure and method of making a board having plating though hole (PTH) core layer substrate and stacked multiple layers of blind vias. More stacking layers of blind vias than conventional methods can be achieved. The fabrication method of the board having high-density core layer includes the following: after the making of the PTH, the filling material filled inside the PTH of the core layer is partially removed until the PTH has reached an appropriate flattened depression using etching; then image transfer and pattern plating are performed to fill and to level the depression portion up to a desired thickness to form a copper pad (overplating) as the core layer substrate is forming a circuit layer; finally using electroless copper deposition and the pattern plating to make the product.

Abstract translation: 制造具有电镀通孔（PTH）芯层衬底和层叠多层盲孔的板的结构和方法。 可以实现比常规方法更多的盲孔堆叠层。 具有高密度芯层的板的制造方法包括以下：在制造PTH之后，填充在芯层的PTH内部的填充材料被部分地去除，直到PTH已经通过蚀刻达到适当的平坦凹陷; 然后进行图像转印和图案电镀，以在芯层基板正在形成电路层时填充并使凹陷部分达到所需厚度以形成铜焊盘（过镀层）; 最后使用无电镀铜和图案电镀制成产品。