公开(公告)号：US20120048600A1

公开(公告)日：2012-03-01

申请号：US12870072

申请日：2010-08-27

Applicant: Matthew S. Doyle ,  Joseph Kuczynski ,  Kevin A. Splittstoesser ,  Timothy J. Tofil

Inventor： Matthew S. Doyle ,  Joseph Kuczynski ,  Kevin A. Splittstoesser ,  Timothy J. Tofil

IPC: H05K1/03 ,  C25D7/00 ,  G03F7/20 ,  G06F17/50 ,  B05D5/12

CPC classification number: H05K1/0296 ,  C25D5/022 ,  C25D5/10 ,  C25D7/00 ,  H05K1/0245 ,  H05K3/18 ,  H05K3/184 ,  H05K2201/09672 ,  H05K2201/098 ,  H05K2203/056 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49155

Abstract: A first artwork layer having a first adaptable-mask section allows a graded amount of light to pass into an underlying first photoresist layer. Subsequent to developing the first photoresist layer, the graded amount of light creates a rounded geometric void used as a mold or sidewall for the creation of at least a lower portion of a rounded trace. A dielectric layer is laminated upon the lower portion and a second artwork layer having an second adaptable-mask section allows a graded amount of light to pass into a second photoresist layer. Subsequent to developing the second photoresist layer, the graded amount of light creates a rounded geometric void used as a mold or sidewall for the creation of at least an upper portion of a rounded trace. The photoresist and dielectric layers are removed resulting in a circuit apparatus having a rounded differential pair trace.

Abstract translation: 具有第一适应性掩模部分的第一艺术品层允许渐变量的光进入下面的第一光致抗蚀剂层。 在显影第一光致抗蚀剂层之后，分级的光产生用作模具或侧壁的圆形几何空隙，用于产生圆形迹线的至少下部。 电介质层层叠在下部，具有第二可适应掩模部分的第二艺术品层允许渐变量的光通过第二光致抗蚀剂层。 在显影第二光致抗蚀剂层之后，分级的光产生用作模具或侧壁的圆形几何空隙，用于至少形成圆形迹线的上部。 去除光致抗蚀剂和介电层，导致具有圆形差分对迹线的电路设备。

公开(公告)号：US08094462B2

公开(公告)日：2012-01-10

申请号：US11998136

申请日：2007-11-28

Applicant: Shozo Miyamoto ,  Makoto Abe

Inventor： Shozo Miyamoto ,  Makoto Abe

IPC: H05K1/11 ,  H05K1/14

CPC classification number: H05K1/0237 ,  H05K1/0219 ,  H05K1/0224 ,  H05K1/0231 ,  H05K1/0253 ,  H05K1/113 ,  H05K9/006 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/09672 ,  H05K2201/10636 ,  Y02P70/611

Abstract: Disclosed is a high frequency tuner module, including: a circuit component; signal lines; a GND line; and a multilayer board formed by laminating a plurality of layers, wherein the circuit component is placed on a top layer surface of the multilayer board; the signal lines and the GND line are formed inside the multilayer board; and among the signal lines, high frequency signal transmitting signal lines to transmit a high frequency signal are formed on a single layer inside the multilayer board.

Abstract translation: 公开了一种高频调谐器模块，包括：电路部件; 信号线 GND线; 以及通过层叠多个层而形成的多层板，其中所述电路部件被放置在所述多层板的顶层表面上; 信号线和GND线形成在多层板内; 并且在信号线中，在多层板内的单层上形成用于发送高频信号的高频信号发送信号线。

公开(公告)号：US20110275247A1

公开(公告)日：2011-11-10

申请号：US13179954

申请日：2011-07-11

Applicant: Frank M. Straka ,  Ronald L. Tellas

Inventor： Frank M. Straka ,  Ronald L. Tellas

IPC: H01R13/66 ,  H01R24/00

CPC classification number: H01R13/6466 ,  H01R4/2425 ,  H01R13/6625 ,  H01R13/6658 ,  H01R24/64 ,  H05K1/0228 ,  H05K1/118 ,  H05K1/147 ,  H05K1/162 ,  H05K2201/09172 ,  H05K2201/09672 ,  H05K2201/10189 ,  Y10S439/941

Abstract: A communication jack has a housing with a face having a plug receiving aperture. A plurality of conductive path pairs extends from corresponding plug interface contacts located at the plug receiving aperture to corresponding output terminals. A first circuit board is connected to the plug interface contacts and a second circuit board is connected to the plug interface contacts and the output terminals. The first circuit board has a first single stage of crosstalk compensation with opposite polarity of the crosstalk of a plug for a first combination of the conductive path pairs. The second circuit board includes a second single stage of opposite polarity crosstalk compensation for some of the conductive path pairs not compensated on the first circuit board. The stages cancel substantially all of the crosstalk caused by the plug, for the signal operating frequencies, for corresponding combinations of the conductive path pairs.

Abstract translation: 通信插座具有带有插头接收孔的面的壳体。 多个导电路径对从位于插头接收孔处的相应插头接口触头延伸到对应的输出端子。 第一电路板连接到插头接口触点，第二电路板连接到插头接口触点和输出端子。 第一电路板具有与导电路径对的第一组合的插头的串扰极性相反的串扰补偿的第一单级。 第二电路板包括用于在第一电路板上未补偿的一些导电路径对的相反极性串扰补偿的第二单级。 针对信号工作频率，对于导电路径对的相应组合，这些级基本上消除了由插头引起的串扰。

公开(公告)号：US08053673B2

公开(公告)日：2011-11-08

申请号：US12068790

申请日：2008-02-12

Applicant: Jin Cheol Kim ,  Tae Kyoung Kim ,  Jun Rok Oh

Inventor： Jin Cheol Kim ,  Tae Kyoung Kim ,  Jun Rok Oh

IPC: H05K1/00

CPC classification number: H05K1/162 ,  H05K3/4602 ,  H05K3/4652 ,  H05K3/4688 ,  H05K2201/09672 ,  H05K2203/061

Abstract: A capacitor embedded printed circuit board (PCB) includes a multilayer polymer capacitor layer with a plurality of polymer sheets. One or more first inner electrodes and second inner electrodes, separated by one or more of the plurality of polymer sheets, are alternately disposed to form a pair. A plurality of first extended electrodes and second extended electrodes protrude from the first inner electrodes and second inner electrodes, respectively. One or more insulating layers are laminated on one or both surfaces of the multilayer polymer capacitor. A plurality of first via holes for capacitor, and a plurality of second via holes for capacitor, penetrating the multilayer polymer capacitor layer are connected to the first extended electrodes and the second extended electrodes, respectively. The plurality of the first and second extended electrodes are alternately disposed to be opposite to each other.

Abstract translation: 电容器嵌入式印刷电路板（PCB）包括具有多个聚合物片的多层聚合物电容层。 由多个聚合物片中的一个或多个隔开的一个或多个第一内部电极和第二内部电极交替地设置成一对。 多个第一延伸电极和第二延伸电极分别从第一内部电极和第二内部电极突出。 在多层聚合物电容器的一个或两个表面上层压一个或多个绝缘层。 多个用于电容器的第一通孔和多个穿过多层聚合物电容器层的电容器用第二通孔分别连接到第一延伸电极和第二延伸电极。 多个第一和第二延伸电极交替地设置成彼此相对。

公开(公告)号：US08040710B2

公开(公告)日：2011-10-18

申请号：US11756541

申请日：2007-05-31

Applicant: Abdallah Bacha

Inventor： Abdallah Bacha

IPC: G11C5/06

CPC classification number: H05K1/181 ,  G06F13/1684 ,  H05K1/0298 ,  H05K2201/09672 ,  H05K2201/10159 ,  H05K2203/1572 ,  Y02P70/611

Abstract: A semiconductor memory arrangement includes a circuit board having at least a first layer and a second layer, a plurality of memory units, and a first control device and a second control device adapted to receive command and address signals. A first bus system is disposed in the first layer of the circuit board and coupled to the first control device and to a first group of memory units of the plurality of memory units to transmit the command and address signals to the first group of memory units. A second bus system is disposed in the second layer of the circuit board and coupled to the second control device and to a second group of memory units of the plurality of memory units to transmit the command and address signals to the second group of memory units.

Abstract translation: 半导体存储器装置包括至少具有第一层和第二层的电路板，多个存储单元，以及适于接收命令和地址信号的第一控制装置和第二控制装置。 第一总线系统被布置在电路板的第一层中，并且耦合到第一控制装置和多个存储器单元中的第一组存储器单元，以将命令和地址信号发送到第一组存储器单元。 第二总线系统被布置在电路板的第二层中，并且耦合到第二控制装置和多个存储器单元中的第二组存储器单元，以将命令和地址信号发送到第二组存储器单元。

公开(公告)号：US20110248380A1

公开(公告)日：2011-10-13

申请号：US13084074

申请日：2011-04-11

Applicant: Shinji YOSHIHARA ,  Kazushi Asami ,  Yasuhiro Kitamura ,  Junji Oohara

Inventor： Shinji YOSHIHARA ,  Kazushi Asami ,  Yasuhiro Kitamura ,  Junji Oohara

IPC: H01L29/86 ,  H01L21/20

CPC classification number: H01L21/6835 ,  H01F5/003 ,  H01F41/041 ,  H01F41/046 ,  H01L2924/0002 ,  H05K1/165 ,  H05K2201/09672 ,  H01L2924/00

Abstract: In a manufacturing method for a semiconductor device having a coil layer part on a substrate, two support substrates each having a flat surface are prepared, and a component member is formed on the flat surface of each of the support substrates. The component member includes a wiring portion having a predetermined pattern and an insulation film surrounding the wiring portion. The wiring portion is provided with a connecting portion exposing from the insulation film. A coil layer part is formed by opposing and bonding the component members formed on the support substrates to each other while applying pressure in a condition where the flat surfaces of the support substrates are parallel to each other. A coil is formed in the coil layer part by connecting the wiring portions through the connecting portions.

Abstract translation: 在具有在基板上具有线圈层部分的半导体器件的制造方法中，准备了具有平坦表面的两个支撑基板，并且在每个支撑基板的平坦表面上形成有部件。 该部件包括具有预定图案的布线部分和围绕布线部分的绝缘膜。 布线部分设置有从绝缘膜露出的连接部分。 线圈层部分通过在支撑基板的平坦表面彼此平行的状态下相对地并且将形成在支撑基板上的部件彼此相对并粘合而形成，同时施加压力。 通过连接部分连接布线部分，在线圈层部分中形成线圈。

公开(公告)号：US08022311B2

公开(公告)日：2011-09-20

申请号：US11797084

申请日：2007-04-30

Applicant: Tae Eui Kim ,  Byoung Youl Min ,  Myung Sam Kang ,  Je Gwang Yoo

Inventor： Tae Eui Kim ,  Byoung Youl Min ,  Myung Sam Kang ,  Je Gwang Yoo

IPC: H05K1/16

CPC classification number: H05K1/162 ,  H05K3/205 ,  H05K3/4626 ,  H05K3/4652 ,  H05K3/4655 ,  H05K3/4688 ,  H05K2201/0209 ,  H05K2201/09672 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49165 ,  Y10T29/49169

Abstract: Disclosed are a printed circuit board for improving the tolerance of embedded capacitors and a method of manufacturing the same. The printed circuit board having embedded capacitors is manufactured by transferring and embedding a circuit layer having a lower electrode formed through an additive process into a resin insulating layer, and thereby is minimized in the circuit tolerance conventionally caused by an etching process to thus be applied to capacitors for RF matching.

Abstract translation: 公开了一种用于提高嵌入式电容器的容限的印刷电路板及其制造方法。 具有嵌入式电容器的印刷电路板通过将具有通过添加工艺形成的下电极的电路层转移并嵌入到树脂绝缘层中而被制造，从而在通常由蚀刻工艺引起的电路容差中被最小化，从而被应用于 电容器用于RF匹配。

公开(公告)号：US20110199165A1

公开(公告)日：2011-08-18

申请号：US12760557

申请日：2010-04-15

Applicant: Ting-Hao Yeh

Inventor： Ting-Hao Yeh

IPC: H01P3/08

CPC classification number: H05K1/025 ,  H05K2201/09354 ,  H05K2201/09672 ,  H05K2201/0979

Abstract: A circuit substrate includes a first pair of ground lines, a second pair of ground lines, a plurality of first connection lines, a plurality of second connection lines and a plurality of conductive pillars. The first and second pairs of ground lines are located on first and second surfaces of the substrate, respecteively. The pillars are located in the substrate and vertically conducted between the first pair of ground lines and the second connection lines and between the second pair of ground lines and the first connection lines, and the first and second pairs of ground lines are conducted, so that a 3-D grounding circuit loop is formed. Moreover, a first pair of signal lines is disposed between the first connection lines for grounding and a second pair of signal lines is disposed between the second connection lines for grounding to get a better signal integrity.

Abstract translation: 电路基板包括第一对接地线，第二对接地线，多个第一连接线，多个第二连接线和多个导电柱。 第一和第二对接地线相对于衬底的第一和第二表面上。 支柱位于基板中，并且在第一对接地线与第二连接线之间以及第二对接地线与第一连接线之间垂直传导，并且第一和第二对接地线被导通，使得 形成3-D接地电路回路。 此外，第一对信号线设置在用于接地的第一连接线之间，并且第二对信号线设置在第二连接线之间用于接地以获得更好的信号完整性。

公开(公告)号：US07985103B2

公开(公告)日：2011-07-26

申请号：US12963090

申请日：2010-12-08

Applicant: Frank M. Straka ,  Ronald L. Tellas

Inventor： Frank M. Straka ,  Ronald L. Tellas

IPC: H01R24/00

CPC classification number: H01R13/6466 ,  H01R4/2425 ,  H01R13/6625 ,  H01R13/6658 ,  H01R24/64 ,  H05K1/0228 ,  H05K1/118 ,  H05K1/147 ,  H05K1/162 ,  H05K2201/09172 ,  H05K2201/09672 ,  H05K2201/10189 ,  Y10S439/941

Abstract: A communication jack has a housing with a face having a plug receiving aperture. A plurality of conductive path pairs extends from corresponding plug interface contacts located at the plug receiving aperture to corresponding output terminals. A first circuit board is connected to the plug interface contacts and a second circuit board is connected to the plug interface contacts and the output terminals. The first circuit board has a first single stage of crosstalk compensation with opposite polarity of the crosstalk of a plug for a first combination of the conductive path pairs. The second circuit board includes a second single stage of opposite polarity crosstalk compensation for some of the conductive path pairs not compensated on the first circuit board. The stages cancel substantially all of the crosstalk caused by the plug, for the signal operating frequencies, for corresponding combinations of the conductive path pairs.

Abstract translation: 通信插座具有带有插头接收孔的面的壳体。 多个导电路径对从位于插头接收孔处的相应插头接口触头延伸到对应的输出端子。 第一电路板连接到插头接口触点，第二电路板连接到插头接口触点和输出端子。 第一电路板具有与导电路径对的第一组合的插头的串扰极性相反的串扰补偿的第一单级。 第二电路板包括用于在第一电路板上未补偿的一些导电路径对的相反极性串扰补偿的第二单级。 针对信号工作频率，对于导电路径对的相应组合，这些级基本上消除了由插头引起的串扰。

公开(公告)号：US07969255B2

公开(公告)日：2011-06-28

申请号：US12265167

申请日：2008-11-05

Applicant: Sung Young Kim ,  Jin Woo Lee

Inventor： Sung Young Kim ,  Jin Woo Lee

IPC: H01P3/08

CPC classification number: H05K1/0219 ,  H05K1/0245 ,  H05K3/4623 ,  H05K2201/09236 ,  H05K2201/09536 ,  H05K2201/09672

Abstract: A printed circuit board (PCB) capable of decreasing wireless wide area network (WWAN) noise generated due to internal signal interference occurring in the PCB is disclosed. The PCB printed circuit board includes a first layer, a second layer, and at least one insulating layer formed between the first and second layers. The PCB board further includes a first signal line group disposed on the first layer while including a plurality of first signal lines each supplying a first signal, isolation patterns disposed on the first layer such that the isolation patterns are arranged between adjacent ones of the first signal lines, respectively, to prevent the adjacent first signal lines from interfering with each other, and a second signal line group disposed on the second layer while including a plurality of second signal lines each supplying a second signal different from the first signal. The second signal line group corresponds to the isolation patterns.

Abstract translation: 公开了能够减少由于PCB内部信号干扰而产生的无线广域网（WWAN）噪声的印刷电路板（PCB）。 PCB印刷电路板包括第一层，第二层和形成在第一层和第二层之间的至少一个绝缘层。 PCB板还包括设置在第一层上的第一信号线组，同时包括多个提供第一信号的第一信号线，设置在第一层上的隔离图案，使得隔离图案布置在相邻的第一信号之间 线路，以防止相邻的第一信号线彼此干扰;以及第二信号线组，其布置在第二层上，同时包括多个第二信号线，每个第二信号线提供与第一信号不同的第二信号。 第二信号线组对应于隔离模式。