公开(公告)号：US20060292769A1

公开(公告)日：2006-12-28

申请号：US11425762

申请日：2006-06-22

Applicant: Kenji Wada ,  Tsuyoshi Shintate

Inventor： Kenji Wada ,  Tsuyoshi Shintate

IPC: H01L21/338

CPC classification number: H05K3/4664 ,  B41M3/006 ,  B41M3/008 ,  H05K3/125 ,  H05K3/4647 ,  H05K2201/09781 ,  H05K2201/09881 ,  H05K2203/013 ,  H05K2203/1476

Abstract: A multilayered structure forming method includes disposing a dummy post on a first insulating pattern as a first inkjet process, disposing a second insulating pattern on the first insulating pattern as a second inkjet process so as to allow the second insulating pattern to surround a side surface of the dummy post, and disposing a first conductive pattern on the second insulating pattern a third inkjet process so as to connect the first conductive pattern to the dummy post. In this method, the first inkjet process includes a process for ejecting a functional liquid containing a first conductive material having high adhesiveness to the first conductive pattern onto the first insulating pattern.

Abstract translation: 多层结构形成方法包括将第一绝缘图案上的虚拟柱设置为第一喷墨处理，将第二绝缘图案设置在第一绝缘图案上作为第二喷墨处理，以使第二绝缘图案包围第二绝缘图案的侧表面 所述虚拟柱，并且在所述第二绝缘图案上设置第一导电图案以进行第三喷墨处理，以将所述第一导电图案连接到所述虚拟柱。 在该方法中，第一喷墨处理包括将含有第一导电图案的具有高粘附性的第一导电材料的功能液喷射到第一绝缘图案上的处理。

公开(公告)号：US07106598B2

公开(公告)日：2006-09-12

申请号：US10865807

申请日：2004-06-14

Applicant: David Liu ,  Chengping Zhang ,  Michael T Duignan

Inventor： David Liu ,  Chengping Zhang ,  Michael T Duignan

IPC: H05K1/00 ,  H05K1/11 ,  H05K7/02

CPC classification number: H05K3/4614 ,  H03H3/00 ,  H03H7/0115 ,  H03H7/06 ,  H03H7/1775 ,  H03H2001/0078 ,  H05K1/16 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/046 ,  H05K3/4069 ,  H05K3/4638 ,  H05K2201/0108 ,  H05K2201/09881 ,  H05K2201/09918 ,  H05K2201/10378 ,  H05K2203/0528 ,  H05K2203/107 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49165

Abstract: A method for manufacturing a modular electrical circuit includes the steps of pre-manufacturing a plurality of components having fine features such as resistors, capacitors, inductances, and conductors formed on a dielectric substrate. The pre-manufactured components are laminated each to the other in a predetermined order. Each pre-manufactured component includes one or more electrical elements of the same type coupled each to the other by conducting lines. Each dielectric substrate includes through vias filled with the conductive material which serve for cross-coupling of the elements of neighboring components. Position of the passive elements, as well as conductive lines and through vias, are pre-designed to allow precise coordination between the elements of different components in the multi-layered modular electrical circuit.

Abstract translation: 一种用于制造模块化电路的方法包括以下步骤：预先制造具有精细特征的部件，例如电阻器，电容器，电感和形成在电介质基片上的导体。 预先制造的部件按预定的顺序彼此分层。 每个预制的部件包括一个或多个相同类型的电气元件，每个通过导线彼此连接。 每个电介质基片包括填充有导电材料的通孔，其用于交叉耦合相邻元件的元件。 无源元件以及导线和通孔的位置被预先设计成允许多层模块化电路中的不同元件的元件之间的精确协调。

公开(公告)号：US20060196691A1

公开(公告)日：2006-09-07

申请号：US11365219

申请日：2006-02-28

Applicant: Jin Ahn ,  Cheol Hwang ,  Sung Kim ,  Chang Ryu ,  Suk Cho ,  Ho Jeon

Inventor： Jin Ahn ,  Cheol Hwang ,  Sung Kim ,  Chang Ryu ,  Suk Cho ,  Ho Jeon

IPC: H05K1/03 ,  H05K1/16 ,  H05K3/06

CPC classification number: H05K1/162 ,  H01L2924/0002 ,  H05K1/095 ,  H05K3/108 ,  H05K3/244 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/09509 ,  H05K2201/09881 ,  Y10S438/957 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/4913 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A printed circuit board having embedded capacitors includes a double-sided copper-clad laminate including first circuit layers formed in the outer layers thereof, the first circuit layers including bottom electrodes and circuit patterns; dielectric layers formed by depositing alumina films on the first circuit layers by atomic layer deposition; second circuit layers formed on the dielectric layers and including top electrodes and circuit patterns; one-sided copper-clad laminates formed on the second circuit layers; blind via-holes and through-holes formed in predetermined portions of the one-sided copper-clad laminates; and plating layers formed in the blind via-holes and the through-holes. The manufacturing method of the printed circuit board is also disclosed.

公开(公告)号：US20060148126A1

公开(公告)日：2006-07-06

申请号：US10537994

申请日：2002-12-12

Applicant: Keiichi Murakami

Inventor： Keiichi Murakami

IPC: H01L21/50 ,  H01L21/31

CPC classification number: H05K3/281 ,  H01L21/4857 ,  H01L23/49822 ,  H01L2924/0002 ,  H05K2201/09881 ,  H05K2203/025 ,  H05K2203/0278 ,  H05K2203/0537 ,  H05K2203/066 ,  H05K2203/085 ,  H05K2203/1152 ,  H05K2203/1536 ,  H01L2924/00

Abstract: There is provided a method for manufacturing a flat printed wiring board in which spaces between circuit patterns are filled with a resin. The method comprises: laminating via a mold release film a plurality of sets of laminated bodies formed by superposing a semi-cured resin sheet on a printed wiring board with circuit patterns formed thereon; placing the laminated plural sets of the laminated bodies interposed between a pair of smoothing plates and collectively pressing the laminated bodies in a reduced pressure atmosphere used for curing the resin; and then polishing the cured resin covering the circuit patterns, thereby exposing the circuit patterns.

Abstract translation: 提供一种制造平板印刷线路板的方法，其中电路图案之间的空间用树脂填充。 该方法包括：通过脱模膜层叠多个层叠体，通过将半固化树脂片叠置在其上形成有电路图案的印刷线路板上形成; 将层叠的多组层叠体置于一对平滑板之间，并在用于固化树脂的减压气氛中一起挤压层叠体; 然后对覆盖电路图案的固化树脂进行抛光，从而露出电路图案。

公开(公告)号：US07033917B2

公开(公告)日：2006-04-25

申请号：US10945961

申请日：2004-09-22

Applicant: Kwun-Yao Ho ,  Moriss Kung

Inventor： Kwun-Yao Ho ,  Moriss Kung

IPC: H01L21/20 ,  H05K3/00

CPC classification number: H01L21/4846 ,  H01L21/486 ,  H05K3/242 ,  H05K3/243 ,  H05K3/28 ,  H05K3/282 ,  H05K3/3457 ,  H05K3/42 ,  H05K2201/0195 ,  H05K2201/09881 ,  H05K2203/054 ,  H05K2203/1581 ,  Y10T29/49124

Abstract: A packaging substrate without plating bar and a method of forming the same is provided. A substrate is firstly provided with circuit patterns formed thereon. Then, solder masks are formed to define connecting points on the circuit patterns. Afterward, the openings of the solder mask on a bottom surface of the substrate are filled with solder material. Thereafter, a seed layer is formed on the bottom surface of the solder mask and the solder material, and then a passivation layer is formed on a surface of the seed layer. Finally, a plating process is carried out by using the seed layer to input cathode electric level to form metal pads on the defined connecting points on the upper surface of the substrate.

Abstract translation: 提供一种不含电镀条的包装基材及其形成方法。 首先在其上形成有电路图案的基板。 然后，形成焊接掩模以限定电路图案上的连接点。 之后，衬底的底面上的焊料掩模的开口被焊料材料填充。 此后，在焊料掩模和焊料材料的底表面上形成种子层，然后在种子层的表面上形成钝化层。 最后，通过使用种子层来进行电镀处理，以输入阴极电平，以在衬底的上表面上限定的连接点上形成金属焊盘。

公开(公告)号：US20060055021A1

公开(公告)日：2006-03-16

申请号：US11084805

申请日：2005-03-18

Applicant: Mitsuhiko Yamamoto

Inventor： Mitsuhiko Yamamoto

IPC: H01L23/48

CPC classification number: H05K1/0265 ,  H01L21/563 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/49894 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/01327 ,  H05K1/036 ,  H05K1/0393 ,  H05K1/111 ,  H05K3/205 ,  H05K3/244 ,  H05K3/245 ,  H05K3/388 ,  H05K3/4644 ,  H05K2201/0376 ,  H05K2201/09727 ,  H05K2201/09736 ,  H05K2201/098 ,  H05K2201/09881 ,  H01L2924/00 ,  H01L2224/0401

Abstract: According to this invention, a wiring board includes a conductive pattern formed from leads each of which is formed on an organic layer and has a thickness t larger than a width W.

Abstract translation: 根据本发明，布线基板包括由引线形成的导电图案，每个引线形成在有机层上并且具有大于宽度W的厚度t

公开(公告)号：US20060044734A1

公开(公告)日：2006-03-02

申请号：US10999442

申请日：2004-11-29

Applicant: Jin-Yong Ahn ,  Chang-Sup Ryu ,  Suk-Hyeon Cho ,  Seok-Kyu Lee ,  Jong-Kuk Hong ,  Ho-Sik Jun

Inventor： Jin-Yong Ahn ,  Chang-Sup Ryu ,  Suk-Hyeon Cho ,  Seok-Kyu Lee ,  Jong-Kuk Hong ,  Ho-Sik Jun

IPC: H01G4/20

CPC classification number: H05K1/162 ,  H01G4/1209 ,  H01G4/1218 ,  H01G4/248 ,  H01G4/33 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0195 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2201/09881 ,  H05K2203/0568 ,  H05K2203/1366 ,  Y10T29/42

Abstract: Disclosed is a PCB including embedded capacitors and a method of fabricating the same. A dielectric layer is formed using a ceramic material having a high capacitance, thereby assuring that the capacitors each have a high dielectric constant corresponding to the capacitance of a decoupling chip capacitor.

Abstract translation: 公开了一种包括嵌入式电容器的PCB及其制造方法。 使用具有高电容的陶瓷材料形成电介质层，从而确保电容器各自具有对应于去耦芯片电容器的电容的高介电常数。

公开(公告)号：US07005318B2

公开(公告)日：2006-02-28

申请号：US10784740

申请日：2004-02-24

Applicant: Kiyokazu Moriizumi ,  Manabu Watanabe

Inventor： Kiyokazu Moriizumi ,  Manabu Watanabe

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H05K3/243 ,  H01L23/49811 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15312 ,  H01L2924/16152 ,  H05K1/113 ,  H05K3/062 ,  H05K3/108 ,  H05K3/28 ,  H05K3/388 ,  H05K3/389 ,  H05K3/467 ,  H05K2201/09845 ,  H05K2201/09881 ,  H05K2203/025 ,  H01L2224/0401

Abstract: A mounted circuit substrate has at least one conductive layer. The side faces of a component mounting pad is formed on a surface of the substrate, and includes at least a columnar pattern made of a metal highly resistant to erosion by solder. The side faces of the component mounting pad are completely covered with an organic insulating layer. Therefore, the component mounting pad can withstand molten solder stresses accompanying component replacement even when component replacement is done many times.

Abstract translation: 安装的电路基板具有至少一个导电层。 元件安装垫的侧面形成在基板的表面上，并且至少包括由金属制成的柱状图案，该金属具有高度耐受焊料侵蚀的金属。 元件安装垫的侧面完全被有机绝缘层覆盖。 因此，即使部件更换多次，组件安装垫也可以承受伴随部件更换的熔融焊料应力。

公开(公告)号：US06995984B2

公开(公告)日：2006-02-07

申请号：US10362722

申请日：2001-06-30

Applicant: Gerd Schmitz

Inventor： Gerd Schmitz

IPC: H05K1/16 ,  H05K3/30

CPC classification number: H05K1/167 ,  H01C17/0652 ,  H05K1/0257 ,  H05K1/095 ,  H05K3/386 ,  H05K2201/0323 ,  H05K2201/09881 ,  H05K2203/1453 ,  Y10T29/49099

Abstract: The invention relates to an electronic assembly, in particular for low power consumption electric switching devices such as low power contactors, time relays or the like. In order to provide protection against input current pulses, an ohmic resistor (6) is provided in the form of a resistive layer that is applied by pressing.

Abstract translation: 本发明涉及一种电子组件，特别涉及低功率电力开关装置，如低功率接触器，时间继电器等。 为了提供针对输入电流脉冲的保护，欧姆电阻器（6）以通过按压施加的电阻层的形式提供。

公开(公告)号：US06954985B2

公开(公告)日：2005-10-18

申请号：US10043146

申请日：2002-01-14

Applicant: Sung Gue Lee ,  Sung Sik Cho ,  Yong Il Kim ,  Yong Soon Jang ,  Ho Sung Choi ,  Sang Jin Kong ,  Young Hwan Kim

Inventor： Sung Gue Lee ,  Sung Sik Cho ,  Yong Il Kim ,  Yong Soon Jang ,  Ho Sung Choi ,  Sang Jin Kong ,  Young Hwan Kim

IPC: H05K3/28 ,  H05K3/00 ,  H05K3/12 ,  H05K3/42 ,  H05K3/46 ,  H01K3/10

CPC classification number: H05K3/0094 ,  H05K3/1225 ,  H05K3/28 ,  H05K2201/09509 ,  H05K2201/0959 ,  H05K2201/09881 ,  H05K2203/0278 ,  H05K2203/0557 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49135 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49167

Abstract: A hole plugging method for a printed circuit board, a hole plugging device in accordance therewith and a manufacturing method in accordance therewith where a mask for selectively exposing a via hole, a through hole and a surface pattern of the printed circuit board is positioned on the board having the via hole and the through hole to electrically connect circuit patterns formed on the surface of the board and in the board and an insulating material is plugged in the via hole by abutting and pushing the material on the surface of the board. Therefore, the insulating material can be plugged smoothly without a void, the processing is simplified by plugging the insulating material just to the height of the circuit pattern in a space between the circuit patterns and accordingly, damage to the circuit pattern can be prevented.

Abstract translation: 用于印刷电路板的孔堵塞方法，根据本发明的孔堵装置及其制造方法，其中用于选择性地暴露印刷电路板的通孔，通孔和表面图案的掩模位于 具有通孔和通孔的电路板电连接板和表面上形成的电路图案和绝缘材料，通过邻接和推动板的表面上的材料而被堵塞在通孔中。 因此，绝缘材料可以没有空隙而平滑地插入，通过将绝缘材料刚好插入电路图案之间的空间中的电路图案的高度来简化处理，因此可以防止电路图案的损坏。