公开(公告)号：US20190206808A1

公开(公告)日：2019-07-04

申请号：US16299358

申请日：2019-03-12

Applicant: DAI NIPPON PRINTING Co., Ltd.

Inventor： Ryohei Kasai ,  Tsuyoshi Tsunoda ,  Yuichi Yamamoto ,  Shuji Sagara ,  Masaya Tanaka

IPC: H01L23/00 ,  H01L21/48 ,  H05K1/18 ,  H05K3/46 ,  H01L23/498 ,  H05K1/02 ,  H01L23/12

CPC classification number: H01L23/562 ,  H01L21/4857 ,  H01L21/4867 ,  H01L23/12 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49866 ,  H05K1/0242 ,  H05K1/0243 ,  H05K1/097 ,  H05K1/18 ,  H05K1/181 ,  H05K3/045 ,  H05K3/1258 ,  H05K3/46 ,  H05K3/4602 ,  H05K2201/0338 ,  H05K2201/0376 ,  H05K2201/09036 ,  H05K2201/09563 ,  H05K2201/10378 ,  H05K2201/10674

Abstract: Disclosed is a wiring substrate including: a first wiring layer, a second wiring layer disposed on the first wiring layer interposed by an insulating film, and a via conductor passing through the insulating film in a thickness direction, the via conductor electrically connecting the first wiring layer and the second wiring layer. The second wiring layer and the via conductor include a second sintered metal layer and a first sintered metal layer arranged to surround the second sintered metal layer, and an average particle diameter of first metal particles forming the first sintered metal layer is smaller than an average particle diameter of second metal particles forming the second sintered metal layer.

公开(公告)号：US20180153036A1

公开(公告)日：2018-05-31

申请号：US15427061

申请日：2017-02-08

Applicant: Unimicron Technology Corp.

Inventor： Ming-Hao Wu ,  Wen-Fang Liu

IPC: H05K1/11 ,  H05K3/00

CPC classification number: H05K1/111 ,  H05K1/115 ,  H05K3/0044 ,  H05K3/3452 ,  H05K3/4697 ,  H05K2201/0376 ,  H05K2203/0228 ,  H05K2203/025

Abstract: A circuit board structure includes an inner circuit structure and a first build-up circuit structure. The inner circuit structure includes a core layer having an upper surface and a lower surface opposite to each other, a first patterned circuit layer disposed on the upper surface, a second patterned circuit layer disposed on the lower surface and a conductive via connecting the first and the second patterned circuit layers. The first build-up circuit structure is disposed on the upper surface of the core layer and covers the first patterned circuit layer, wherein the first build-up circuit structure at least has a cavity, the cavity exposes a portion of the first patterned circuit layer and a cross-sectional profile of an edge of a top surface of the portion of the first patterned circuit layer exposed by the cavity is a curved surface.

公开(公告)号：US09970648B2

公开(公告)日：2018-05-15

申请号：US15153053

申请日：2016-05-12

Applicant: LG ELECTRONICS INC.

Inventor： Jaepyo Hong ,  Jaechan Kim ,  Injoong Kim ,  Hyeuk Chang ,  Sumin Jun

IPC: F21S4/00 ,  F21V29/74 ,  H01L33/64 ,  H05K1/05 ,  H01L33/62 ,  F21Y101/02 ,  H05K3/28

CPC classification number: F21V29/74 ,  F21Y2101/00 ,  H01L33/62 ,  H01L33/64 ,  H01L33/647 ,  H05K1/053 ,  H05K3/28 ,  H05K2201/0376 ,  H05K2201/10106 ,  H05K2201/2054 ,  H05K2203/1355

Abstract: A light source module includes at least one light source, and a body supporting the light source. The body includes a heat sink supporting the light source on a top surface thereof, the heat sink absorbing heat from the light source and dissipating the heat to the outside, an insulating layer provided on at least one surface of the heat sink, the insulating layer having electrical insulating properties, and a conductive layer provided on the insulating layer. The conductive layer includes connection regions through which electric current is supplied to the light source, and a light source region disposed between the connection regions, the light source region having the light source mounted therein. A protective layer is stacked in the connection region. Accordingly, it is possible to obtain effects such as rapid fabrication processes, inexpensive fabrication cost, facilitation of mass production, improvement of product yield, protection of a conductive material, improvement of the lifespan of products, and enhancement of the stability of products.

公开(公告)号：US09961768B2

公开(公告)日：2018-05-01

申请号：US14919058

申请日：2015-10-21

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yoshihito Otsubo ,  Toru Meguro ,  Tatsunori Kan

IPC: H05K1/00 ,  H05K1/09 ,  H05K1/11 ,  H05K3/40 ,  H05K3/46 ,  H05K1/02 ,  H05K3/00 ,  H05K3/42 ,  H01L23/498 ,  H01L21/48 ,  H05K3/34

CPC classification number: H05K1/09 ,  H01L21/4867 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/19105 ,  H05K1/0298 ,  H05K1/112 ,  H05K1/115 ,  H05K3/0058 ,  H05K3/3436 ,  H05K3/4038 ,  H05K3/4084 ,  H05K3/42 ,  H05K3/4629 ,  H05K3/4644 ,  H05K3/4667 ,  H05K2201/0376 ,  H05K2201/0382 ,  H05K2201/09545 ,  H05K2201/09627 ,  H05K2201/09836 ,  H05K2201/09845 ,  H05K2201/1006 ,  H05K2203/0278 ,  H05K2203/063 ,  H05K2203/068 ,  H05K2203/1126 ,  H01L2924/00

Abstract: A multilayer wiring substrate that can realize a higher-density wiring structure is obtained. Provided is a multilayer wiring substrate, where a multilayer body including a first insulating layer and a second insulating layer stacked on the bottom surface of the first insulating layer includes printed wiring electrodes; the printed wiring electrodes are formed by printing with and sintering conductive paste; the printed wiring electrodes respectively include first wiring electrode portions located on the second insulating layer and second wiring electrode portions respectively joined to first wiring electrode portions; and the second wiring electrode portions respectively extend into through holes and, further, are exposed at the top surface of the first insulating layer.

公开(公告)号：US20180098436A1

公开(公告)日：2018-04-05

申请号：US15821532

申请日：2017-11-22

Applicant: Intel Corporation

Inventor： Qinglei Zhang

IPC: H05K3/24 ,  H01L21/48

CPC classification number: H05K3/244 ,  H01L21/4857 ,  H01L23/13 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/81444 ,  H01L2224/81801 ,  H01L2924/12042 ,  H05K3/282 ,  H05K3/3436 ,  H05K2201/0376 ,  H05K2201/10378 ,  H05K2201/10734 ,  H05K2203/025 ,  H05K2203/1476 ,  H05K2203/1572 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/014

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for dual surface finish package substrate assemblies. In one embodiment a method includes depositing a first surface finish on one or more electrical routing features located on a first side of a package substrate and on one or more lands located on a second side of the package substrate, the second side being opposite the first side of the substrate. The method may further include removing the first surface finish on the first side of the package substrate; and depositing a second surface finish on the one or more electrical routing features of the first side. The depositing of the second surface finish may be accomplished by one of a Direct Immersion Gold (DIG) process or an Organic Solderability Preservative (OSP) process. Other embodiments may be described and/or claimed.

公开(公告)号：US20180063950A1

公开(公告)日：2018-03-01

申请号：US15799591

申请日：2017-10-31

Applicant: JX NIPPON MINING & METALS CORPORATION

Inventor： Michiya KOHIKI

IPC: H05K1/09 ,  H05K3/42 ,  H05K3/40 ,  H05K3/02

CPC classification number: H05K1/09 ,  C23C18/1653 ,  C25D1/04 ,  C25D3/04 ,  C25D3/18 ,  C25D3/38 ,  C25D3/562 ,  C25D5/14 ,  C25D7/0614 ,  H05K3/0058 ,  H05K3/025 ,  H05K3/205 ,  H05K3/4007 ,  H05K3/421 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/09509 ,  H05K2203/0152 ,  H05K2203/0156 ,  H05K2203/0307 ,  H05K2203/0723 ,  H05K2203/0726

Abstract: Provided is a copper foil provided with a carrier in which the laser hole-opening properties of the ultrathin copper layer are good and which is suitable for producing a high-density integrated circuit substrate. A copper foil provided with a carrier having, in order, a carrier, an intermediate layer, and an ultrathin copper layer, wherein the specular gloss at 60° in an MD direction of the intermediate layer side surface of the ultrathin copper layer is 140 or less.

公开(公告)号：US20180053736A1

公开(公告)日：2018-02-22

申请号：US15795511

申请日：2017-10-27

Applicant: ROHM CO., LTD.

Inventor： Takuma SHIMOICHI ,  Yasuhiro KONDO

IPC: H01L23/66 ,  H01L49/02 ,  H01L27/01

CPC classification number: H01L23/66 ,  H01L27/016 ,  H01L28/10 ,  H01L28/20 ,  H01L28/60 ,  H01L2223/6672 ,  H01L2924/0002 ,  H05K1/0289 ,  H05K1/029 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/107 ,  H05K3/146 ,  H05K2201/0317 ,  H05K2201/0338 ,  H05K2201/0376 ,  H05K2201/0391 ,  H05K2201/09263 ,  H05K2201/09981 ,  H05K2201/10181 ,  H05K2203/0353 ,  H05K2203/1338 ,  H01L2924/00

Abstract: A chip part includes a substrate, a first electrode and a second electrode which are formed apart from each other on the substrate and a circuit network which is formed between the first electrode and the second electrode. The circuit network includes a first passive element including a first conductive member embedded in a first trench formed in the substrate and a second passive element including a second conductive member formed on the substrate outside the first trench.

公开(公告)号：US20180027667A1

公开(公告)日：2018-01-25

申请号：US15550086

申请日：2015-12-21

Applicant: Robert Bosch GmbH

Inventor： Harun Bueyuekgoez ,  Roland Gerstner ,  Josef Weber

IPC: H05K3/46 ,  H05K1/11 ,  H05K3/40 ,  H05K1/02

CPC classification number: H05K3/4629 ,  H05K1/0204 ,  H05K1/0206 ,  H05K1/115 ,  H05K3/4046 ,  H05K2201/0376 ,  H05K2201/10416

Abstract: The invention relates to a circuit carrier (1) comprising a plurality of inorganic substrate layers (1.1) that have partial metallisations (1.2, 1.3, 1.4, 1.5, 1.6) for the purpose of electrical and/or thermal conduction, and to a corresponding method for producing such a circuit carrier (1). According to the invention, at least one partial metallisation is made in the form of an insert (1.2) that fills a corresponding shaped hole (1.7) introduced into one of said inorganic substrate layers (1.1).

公开(公告)号：US09814129B2

公开(公告)日：2017-11-07

申请号：US15184511

申请日：2016-06-16

Applicant: LG INNOTEK CO., LTD.

Inventor： Yong Seok Cho ,  Chang Sung Kim

IPC: H05K1/02 ,  H05K1/09 ,  H05K3/46 ,  H05K3/28

CPC classification number: H05K1/0203 ,  H05K1/0209 ,  H05K1/0227 ,  H05K1/09 ,  H05K3/28 ,  H05K3/4644 ,  H05K2201/0376 ,  H05K2201/09227 ,  H05K2201/09881

Abstract: Disclosed is a printed circuit board. The printed circuit board includes an insulating layer, a copper foil formed on the insulating layer and formed therein with a groove to expose a portion of a top surface of the insulating layer, and a thermal conductive layer filled in the groove.

公开(公告)号：US20170311443A1

公开(公告)日：2017-10-26

申请号：US15138261

申请日：2016-04-26

Applicant: Kinsus Interconnect Technology Corp.

Inventor： Ting-Hao LIN ,  Chiao-Cheng Chang ,  Yi-Nong Lin

IPC: H05K1/02 ,  H05K3/10 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K3/42 ,  H05K1/0284 ,  H05K1/0296 ,  H05K1/112 ,  H05K3/007 ,  H05K3/4647 ,  H05K2201/0376 ,  H05K2203/0733 ,  H05K2203/1476 ,  Y10T29/49165

Abstract: Provided is a double layer circuit board and a manufacturing method thereof. The double layer circuit board comprises a substrate, a first circuit layer formed on a first surface of the substrate, a second circuit layer formed on a second surface of the substrate, and at least one connecting pillar formed in and covered by the substrate. Each one of the at least one connecting pillar includes a first end connected to the first circuit layer and a second end connected to the second circuit layer. A terminal area of the second end is greater than a terminal area of the first end. Therefore, the second circuit layer is firmly connected to the first circuit layer through the at least one connecting pillar. A yield rate of the double layer circuit board may be increased.