公开(公告)号：US10770372B2

公开(公告)日：2020-09-08

申请号：US15274335

申请日：2016-09-23

Applicant: Altera Corporation

Inventor： Ravi Gutala ,  Arif Rahman ,  Aravind Dasu ,  Thomas Sarvey ,  Devdatta Kulkarni

IPC: H01L23/473 ,  H01L23/367 ,  H01L23/46 ,  H01L23/34 ,  G06F1/20 ,  G06F30/39 ,  G06F30/398 ,  H01L21/48 ,  H01L23/40 ,  G06F119/08

Abstract: A fluid routing device includes a fluid inlet, first vertical channels, a horizontal channel, a second vertical channel, and a fluid outlet. The first vertical channels are open to the fluid inlet. The horizontal channel is open to each of the first vertical channels. The first vertical channels are oriented to provide fluid coolant from the fluid inlet vertically down to the horizontal channel. The horizontal channel is open on one side such that fluid coolant in the horizontal channel directly contacts an apparatus attached to a bottom of the fluid routing device. The second vertical channel is open to the horizontal channel. The second vertical channel is oriented to provide fluid coolant vertically up away from the horizontal channel. The fluid outlet is open to the second vertical channel such that fluid coolant from the second vertical channel exits the fluid routing device through the fluid outlet.

公开(公告)号：US10762013B2

公开(公告)日：2020-09-01

申请号：US16532193

申请日：2019-08-05

Applicant: ALTERA CORPORATION

Inventor： Sita Rama Chandrasekhar Mallela ,  Yu Ying Choo

IPC: G06F13/32 ,  G06F13/22

Abstract: Devices and methods of providing drivers for software and hardware systems to avoid additional polling or interrupt mechanisms are provided. An electronic device includes a processor supporting a device driver to perform a data packet receiving operation or data packet transmission operation. The device driver causes the processor to receive one or more data packets to a port of the processor according to a time-synchronization protocol. The device driver polls the DMA feature for a completion status of the storing. The device driver causes the processor to determine a timestamp of the one or more data packets and to complete the data packet receiving operation without the device driver causing the processor to perform a polling operation or an interrupt operation to retrieve the timestamp of the one or more data packets.

公开(公告)号：US10761805B2

公开(公告)日：2020-09-01

申请号：US16143234

申请日：2018-09-26

Applicant: ALTERA CORPORATION

Inventor： Martin Langhammer

IPC: G06F7/487 ,  G06F9/30 ,  G06F7/485 ,  G06F17/16 ,  G06F7/499 ,  G06F7/544

Abstract: The present embodiments relate to performing reduced-precision floating-point arithmetic operations using specialized processing blocks with higher-precision floating-point arithmetic circuitry. A specialized processing block may receive four floating-point numbers that represent two single-precision floating-point numbers, each separated into an LSB portion and an MSB portion, or four half-precision floating-point numbers. A first partial product generator may generate a first partial product of first and second input signals, while a second partial product generator may generate a second partial product of third and fourth input signals. A compressor circuit may generate carry and sum vector signals based on the first and second partial products; and circuitry may anticipate rounding and normalization operations by generating in parallel based on the carry and sum vector signals at least two results when performing the single-precision floating-point operation and at least four results when performing the two half-precision floating-point operations.

公开(公告)号：US20200257839A1

公开(公告)日：2020-08-13

申请号：US16859732

申请日：2020-04-27

Applicant: Altera Corporation

Inventor： Junaid Asim Khan ,  Gabriel Quan ,  Ketan Padalia ,  Scott James Brissenden ,  Ryan Fung

IPC: G06F30/327 ,  G06F30/392 ,  G06F30/394

Abstract: A method for implementing physical optimizations includes performing physical optimizations on a first reference version of a design, maintaining a computer-readable list of the physical optimizations, and during a subsequent compile for a second version of the design: identifying matching cells, nets, or both between the first reference version of the design and the second version of the design; and restoring at least a subset of the physical optimizations in the second version of the design by reading the computer-readable list of the physical optimizations and applying the subset to a computer-readable description of the second version of the design.

公开(公告)号：US10726328B2

公开(公告)日：2020-07-28

申请号：US14879928

申请日：2015-10-09

Applicant: Altera Corporation

Inventor： Andrew Chaang Ling ,  Gordon Raymond Chiu ,  Utku Aydonat

IPC: G06N3/063 ,  G06N3/04

Abstract: A method for implementing a convolutional neural network (CNN) accelerator on a target includes identifying characteristics and parameters for the CNN accelerator. Resources on the target are identified. A design for the CNN accelerator is generated in response to the characteristics and parameters of the CNN accelerator and the resources on the target.

公开(公告)号：US20200183877A1

公开(公告)日：2020-06-11

申请号：US16792507

申请日：2020-02-17

Applicant: Altera Corporation

Inventor： Gary Brian Wallichs ,  Keith Duwel ,  Cora Lynn Mau

IPC: G06F13/42 ,  G06F5/06 ,  H04L29/06

Abstract: Systems and methods are provided for supporting wide-protocol interface across a multi-die interconnect interface. Data signals of a wide-protocol interface are split into a plurality of data streams. A handshake signal is established between a first circuit and a second circuit, whereby the first circuit and second circuit are dies of a multi-die device. The first circuit transmits the plurality of data streams to the second circuit via a plurality of multi-die interconnect channels. Each data stream of the plurality of data streams are compressed based on the handshake signal in order to provide wide-protocol interface with reduced number of required pins.

公开(公告)号：US10671790B2

公开(公告)日：2020-06-02

申请号：US15790009

申请日：2017-10-22

Applicant: Altera Corporation

Inventor： Mahesh A. Iyer

IPC: G06F30/30 ,  G06F30/398

Abstract: A method for designing a system on a target device includes performing register retiming on an original design for the system to generate a retimed design. Whether the retimed design is structurally correct is verified by performing register retiming on the retimed design.

公开(公告)号：US10671781B2

公开(公告)日：2020-06-02

申请号：US15951127

申请日：2018-04-11

Applicant: Altera Corporation

Inventor： Salem Derisavi ,  Gordon Raymond Chiu ,  Benjamin Gamsa ,  David Ian M. Milton

IPC: G06F30/30 ,  G06F30/3312 ,  G06F30/327 ,  G06F30/398 ,  G06F119/12

Abstract: A method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components affected by the timing exception. Register retiming is performed where pipeline registers are added at boundaries of the area.

公开(公告)号：US10649731B2

公开(公告)日：2020-05-12

申请号：US16168667

申请日：2018-10-23

Applicant: Altera Corporation

Inventor： Martin Langhammer

IPC: G06F17/14 ,  G06F7/483 ,  G06F7/48 ,  G06F7/544

Abstract: Integrated circuits with specialized processing blocks are provided. A specialized processing block may include one real addition stage and one real multiplier stage. The multiplier stage may simultaneously feed its output to the addition stage and directly to an adjacent specialized processing block. The addition stage may also produce sum and difference outputs in parallel. A group of four such specialized processing blocks may be connected in a chain to implement a radix-2 fast Fourier transform (FFT) butterfly. Multiple radix-2 butterflies may be stacked to form yet higher order radix butterflies. If desired, the specialized processing block may also be used to implement a complex multiply operation. Three or four specialized processing blocks may be chained together and along with one or more adders outside the specialized processing blocks, real and imaginary portions of a complex product can be generated.

公开(公告)号：US10591544B2

公开(公告)日：2020-03-17

申请号：US16043035

申请日：2018-07-23

Applicant: Altera Corporation

Inventor： Dana How ,  Dinesh Patil ,  Arifur Rahman ,  Jeffrey Erik Schulz

IPC: G06F11/20 ,  G06F11/16 ,  G01R31/3185 ,  G06F11/18 ,  G06F11/00 ,  G01R31/28 ,  H01L25/065

Abstract: Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a master die that is coupled to one or more slave dies via inter-die package interconnects. A mixed (i.e., active and passive) interconnect redundancy scheme may be implemented to help repair potentially faulty interconnects to improve assembly yield. Interconnects that carry normal user signals may be repaired using an active redundancy scheme by selectively switching into use a spare driver block when necessary. On the other hand, interconnects that carry power-on-reset signals, initialization signals, and other critical control signals for synchronizing the operation between the master and slave dies may be supported using a passive redundancy scheme by using two or more duplicate wires for each critical signal.