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    Deposition film orientation and reflectivity improvement using a self-aligning ultra-thin layer
    21.
    发明授权
    Deposition film orientation and reflectivity improvement using a self-aligning ultra-thin layer 失效
    使用自对准超薄层的沉积膜取向和反射率提高

    公开(公告)号：US6120844A

    公开(公告)日：2000-09-19

    申请号：US622941

    申请日：1996-03-27

    Applicant: Liang Chen ,  Ted Guo ,  Fusen Chen ,  Roderick C. Mosely

    Inventor： Liang Chen ,  Ted Guo ,  Fusen Chen ,  Roderick C. Mosely

    IPC: H01L21/28 ,  C23C14/56 ,  C23C16/54 ,  H01L21/02 ,  H01L21/203 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/677 ,  H01L21/768 ,  C23C14/34 ,  C23C16/06 ,  C23C16/22

    CPC classification number: H01L21/76876 ,  C23C14/568 ,  C23C16/54 ,  H01L21/32051 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76879

    Abstract: The present invention relates generally to an improved apparatus and process to provide a thin self-aligning layer prior to forming a conducting film layer thereover to improve the film characteristics and deposition coverage. In one aspect of the invention, a dielectric layer is formed over a conducting or semiconducting layer and etched to form an aperture exposing the underlying conducting or semiconducting layer on the aperture floor. An ultra-thin nucleation layer is then deposited by either vapor deposition or chemical vapor deposition onto the field of the dielectric layer. A CVD metal layer is then deposited onto the structure to achieve selective deposition on the floor of the aperture, while preferably also forming a highly oriented blanket layer on the field. In another aspect of the invention, a thin, self-aligning layer is formed over a barrier layer prior to deposition of a conducting film thereover. It is believed that the self-aligning layer enhances the reflectivity of the films by improving the crystal structure in the resulting film and provides improved electromigration performance by providing crystal orientation. The process is preferably carried out in an integrated processing system that includes both a PVD and CVD processing chamber so that once the substrate is introduced into a vacuum environment, the process occurs without the formation of oxides between the layers.

    Abstract translation: 本发明一般涉及在形成导电膜层之前提供薄的自对准层以改善膜特性和沉积覆盖的改进的装置和工艺。 在本发明的一个方面，电介质层形成在导电或半导体层之上，并被蚀刻以形成露出孔底板上下面的导电或半导体层的孔。 然后通过气相沉积或化学气相沉积将超薄成核层沉积到电介质层的场上。 然后将CVD金属层沉积到结构上以实现孔的地板上的选择性沉积，同时优选地还在场上形成高度取向的覆盖层。 在本发明的另一方面，在其上沉积导电膜之前，在阻挡层上方形成薄的自对准层。 据认为，通过改善所得膜中的晶体结构，自对准层增强了膜的反射率，并通过提供<111>晶体取向来提供改善的电迁移性能。 该方法优选在包括PVD和CVD处理室的集成处理系统中进行，使得一旦将基底引入真空环境中，则该过程发生而不在层之间形成氧化物。

    Single step process for blanket-selective CVD aluminum deposition
    22.
    发明授权
    Single step process for blanket-selective CVD aluminum deposition 失效
    毯式选择性CVD铝沉积的单步法

    公开(公告)号：US6077781A

    公开(公告)日：2000-06-20

    申请号：US620405

    申请日：1996-03-22

    Applicant: Ted Guo ,  Liang-Yuh Chen ,  Mehul Naik ,  Roderick C. Mosely

    Inventor： Ted Guo ,  Liang-Yuh Chen ,  Mehul Naik ,  Roderick C. Mosely

    IPC: H01L21/285 ,  C23C14/56 ,  C23C16/54 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/677 ,  H01L21/768 ,  H01L23/522 ,  H01L21/44

    CPC classification number: C23C14/568 ,  C23C16/54 ,  H01L21/32051 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879

    Abstract: The present invention relates generally to an improved apparatus and process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron aperture width applications. In one aspect of the invention, a dielectric layer is formed over a conducting member. A thin nucleation layer is then deposited onto the dielectric layer prior to etching high aspect ratio apertures through the nucleation and dielectric layers to expose the underlying conducting member on the aperture floor. A CVD metal layer is then deposited onto the structure to achieve selective deposition within the apertures, while preferably also forming a blanket layer on the field. The present apparatus and process reduce the number of steps necessary to fabricate CVD metal interconnects and layers that are substantially void-free and planarized. The metallization process is preferably carried out in an integrated processing system that includes both a PVD and CVD processing chamber so that once the substrate is introduced into a vacuum environment, the metallization of the apertures to form vias and contacts occurs without the formation of oxides between the layers.

    Abstract translation: 本发明一般涉及一种改进的装置和方法，用于在衬底上提供均匀的台阶覆盖和金属层的平坦化，以在半微米孔径宽度应用中形成连续的无空隙触点或通孔。 在本发明的一个方面中，在导电部件上形成电介质层。 然后在蚀刻通过成核和电介质层的高纵横比孔之前将薄的成核层沉积到介电层上，以露出孔底板上的下面的导电构件。 然后将CVD金属层沉积到结构上以实现孔内的选择性沉积，同时优选地还在场上形成覆盖层。 本装置和工艺减少了制造基本上无空隙和平坦化的CVD金属互连和层所需的步骤数量。 金属化处理优选在包括PVD和CVD处理室的一体化处理系统中进行，使得一旦将衬底引入真空环境中，孔的金属化形成通孔和接触，而不会在两者之间形成氧化物之间 层。

    Collimation hardware with RF bias rings to enhance sputter and/or substrate cavity ion generation efficiency
    24.
    发明授权
    Collimation hardware with RF bias rings to enhance sputter and/or substrate cavity ion generation efficiency 失效
    准直硬件具有RF偏置环，以增强溅射和/或衬底腔体离子产生效率

    公开(公告)号：US5431799A

    公开(公告)日：1995-07-11

    申请号：US145744

    申请日：1993-10-29

    Applicant: Roderick C. Mosely ,  Ivo J. Raaijmakers ,  Hiroji Hanawa

    Inventor： Roderick C. Mosely ,  Ivo J. Raaijmakers ,  Hiroji Hanawa

    IPC: C23C14/34 ,  H01J37/34 ,  H01L21/203

    CPC classification number: H01J37/32082 ,  H01J37/3405 ,  H01J37/3438 ,  H01J2237/3327

    Abstract: A plasma deposition system for sputter depositing material from a target onto a wafer, the system including a vacuum chamber; a platform for holding the wafer during plasma processing; a source onto which the target is mounted and for generating a plasma in the chamber during operation; an equipotential conductive plane dividing the chamber into an upper cavity in which the target is located and a lower cavity in which the wafer is located, the equipotential conductive plane permitting material sputtered from the target to pass therethrough; and an upper antenna located inside the upper cavity and surrounding the plasma, the upper antenna for coupling RF power into the source-generated plasma.

    Abstract translation: 一种等离子体沉积系统，用于将材料从目标溅射沉积到晶片上，所述系统包括真空室; 用于在等离子体处理期间保持晶片的平台; 其上安装有目标物的源和用于在操作期间在腔室中产生等离子体; 等离子导电平面将腔室分成其中靶位于其中的上空腔和晶片所位于的下空腔，等电位导电平面允许从靶溅射的材料通过; 以及位于上腔体内并围绕等离子体的上天线，用于将RF功率耦合到源产生的等离子体的上天线。

    End point detection for sputtering and resputtering
    27.
    发明授权
    End point detection for sputtering and resputtering 失效
    溅射和再溅射的终点检测

    公开(公告)号：US07048837B2

    公开(公告)日：2006-05-23

    申请号：US10659902

    申请日：2003-09-11

    Applicant: Sasson R. Somekh ,  Marc O. Schweitzer ,  John C. Forster ,  Zheng Xu ,  Roderick C. Mosely ,  Barry L. Chin ,  Howard E. Grunes

    Inventor： Sasson R. Somekh ,  Marc O. Schweitzer ,  John C. Forster ,  Zheng Xu ,  Roderick C. Mosely ,  Barry L. Chin ,  Howard E. Grunes

    IPC: C23C14/35

    CPC classification number: C23C14/544 ,  C23C14/046 ,  C23C14/165 ,  C23C14/5833 ,  C23C14/5873 ,  G01N21/68 ,  H01J37/321 ,  H01J37/32477 ,  H01J37/32935 ,  H01J37/32963 ,  H01J37/3455 ,  H01L21/2855 ,  H01L21/76814 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L22/26 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Plasma etching or resputtering of a layer of sputtered materials including opaque metal conductor materials may be controlled in a sputter reactor system. In one embodiment, resputtering of a sputter deposited layer is performed after material has been sputtered deposited and while additional material is being sputter deposited onto a substrate. A path positioned within a chamber of the system directs light or other radiation emitted by the plasma to a chamber window or other optical view-port which is protected by a shield against deposition by the conductor material. In one embodiment, the radiation path is folded to reflect plasma light around the chamber shield and through the window to a detector positioned outside the chamber window. Although deposition material may be deposited onto portions of the folded radiation path, in many applications, the deposition material will be sufficiently reflective to permit the emission spectra to be detected by a spectrometer or other suitable detector without significant signal loss. The etching or resputtering may be terminated when the detector detects that an underlying layer has been reached or when some other suitable process point has been reached.

    Abstract translation: 可以在溅射反应器系统中控制包括不透明金属导体材料的溅射材料层的等离子体蚀刻或再溅射。 在一个实施例中，溅射沉积层的溅射在材料溅射沉积之后进行，并且另外的材料被溅射沉积到衬底上。 位于系统的腔室内的路径将等离子体发射的光或其他辐射引导到腔室窗口或其他光学视图端口，其被屏蔽物保护以防止被导体材料沉积。 在一个实施例中，辐射路径被折叠以将等离子体光围绕室屏蔽件并且通过窗口反射到位于室窗口外部的检测器。 虽然沉积材料可以沉积在折叠辐射路径的部分上，但是在许多应用中，沉积材料将被充分反射，以允许发射光谱由光谱仪或其它合适的检测器检测，而没有显着的信号损失。 当检测器检测到已经到达下层或者当达到某些其它合适的处理点时，蚀刻或再溅射可以被终止。

    Construction of a film on a semiconductor wafer
    29.
    发明授权
    Construction of a film on a semiconductor wafer 失效
    在半导体晶片上构造膜

    公开(公告)号：US06251758B1

    公开(公告)日：2001-06-26

    申请号：US08810221

    申请日：1997-02-28

    Applicant: Chyi Chern ,  Michal Danek ,  Marvin Liao ,  Roderick C. Mosely ,  Karl Littau ,  Ivo Raaijmakers ,  David C. Smith

    Inventor： Chyi Chern ,  Michal Danek ,  Marvin Liao ,  Roderick C. Mosely ,  Karl Littau ,  Ivo Raaijmakers ,  David C. Smith

    IPC: H01L2128

    CPC classification number: H01L21/76864 ,  C23C16/34 ,  C23C16/45565 ,  C23C16/4581 ,  C23C16/4586 ,  C23C16/481 ,  C23C16/5096 ,  C23C16/56 ,  H01J37/32174 ,  H01J2237/2001 ,  H01J2237/336 ,  H01L21/28512 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76862

    Abstract: The construction of a film on a wafer, which is placed in a processing chamber, may be carried out through the following steps. A layer of material is deposited on the wafer. Next, the layer of material is annealed. Once the annealing is completed, the material may be oxidized. Alternatively, the material may be exposed to a silicon gas once the annealing is completed. The deposition, annealing, and either oxidation or silicon gas exposure may all be carried out in the same chamber, without need for removing the wafer from the chamber until all three steps are completed. A semiconductor wafer processing chamber for carrying out such an in-situ construction may include a processing chamber, a showerhead, a wafer support and a rf signal means. The showerhead supplies gases into the processing chamber, while the wafer support supports a wafer in the processing chamber. The rf signal means is coupled to the showerhead and the wafer support for providing a first rf signal to the showerhead and a second rf signal to the wafer support.

    Abstract translation: 放置在处理室中的晶片上的膜的构造可以通过以下步骤进行。 在晶片上沉积一层材料。 接下来，将材料层退火。 一旦退火完成，材料可能被氧化。 或者，一旦退火完成，材料可能暴露于硅气体。 沉积，退火和氧化或硅气体暴露都可以在相同的室中进行，而不需要从腔室中移除晶片，直到完成所有三个步骤。 用于进行这种原位结构的半导体晶片处理室可以包括处理室，喷头，晶片支架和射频信号装置。 淋浴头将气体供应到处理室中，而晶片支撑件在处理室中支撑晶片。 rf信号装置耦合到喷头和晶片支架，用于向喷头提供第一rf信号，并将第二rf信号耦合到晶片支架。

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