公开(公告)号：US06828669B2

公开(公告)日：2004-12-07

申请号：US09736864

申请日：2000-12-14

Applicant: Takahiro Iijima ,  Shinichi Wakabayashi ,  Yuichi Matsuda

Inventor： Takahiro Iijima ,  Shinichi Wakabayashi ,  Yuichi Matsuda

IPC: H01L2312

CPC classification number: H01L24/12 ,  H01L21/76885 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13021 ,  H01L2224/13099 ,  H01L2224/16237 ,  H01L2224/81385 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15787 ,  H05K1/0271 ,  H05K1/111 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/09736 ,  H05K2201/0989 ,  H05K2201/10674 ,  H05K2203/0597 ,  Y02P70/611 ,  Y10S428/901 ,  Y10T29/49126 ,  H01L2924/00 ,  H01L2224/05599

Abstract: An interconnection substrate comprises an uppermost interconnection layer having a plurality of terminal pads located at positions corresponding to a plurality of solder bumps (external connection terminals) provided on a semiconductor element which is to be mounted on the interconnection substrate. The interconnection substrate also has a metal column formed on each of the terminal pads and has a resin film covering a side surface of the metal column. The interconnection substrate further has an insulating layer formed on the uppermost interconnection layer so that a gap is formed between the insulating layer and an outer peripheral surface of the resin film.

Abstract translation: 互连基板包括最上面的互连层，其具有位于与要安装在互连基板上的半导体元件上的多个焊料凸块（外部连接端子）对应的位置处的多个端子焊盘。 互连基板还具有形成在每个端子焊盘上的金属柱，并且具有覆盖金属柱的侧表面的树脂膜。 互连衬底还具有形成在最上层的互连层上的绝缘层，从而在绝缘层和树脂膜的外周表面之间形成间隙。

公开(公告)号：US20120327626A1

公开(公告)日：2012-12-27

申请号：US13528987

申请日：2012-06-21

Applicant: Michio Horiuchi ,  Yasue Tokutake ,  Yuichi Matsuda ,  Tomoo Yamasaki

Inventor： Michio Horiuchi ,  Yasue Tokutake ,  Yuichi Matsuda ,  Tomoo Yamasaki

IPC: H05K1/02 ,  H05K3/00 ,  H05K7/06

CPC classification number: H01L21/486 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/4602 ,  H05K2201/10378 ,  Y10T29/49124 ,  H01L2924/00

Abstract: One embodiment provides a wiring substrate including: a core substrate having an insulative base member, the insulative base member having a first surface and a second surface, a plurality of linear conductors penetrating through the insulative base member from the first surface to the second surface; an inorganic material layer joined to at least one of the first surface and the second surface of the insulative base member; and a penetration line penetrating through the inorganic material layer, wherein one end of the penetration line is electrically connected to a corresponding part of the linear conductors, without intervention of a bump.

Abstract translation: 一个实施例提供一种布线基板，包括：具有绝缘基底构件的芯基板，所述绝缘基底构件具有第一表面和第二表面;多个线状导体，从所述第一表面穿过所述绝缘基底构件到所述第二表面; 连接到所述绝缘基体的第一表面和所述第二表面中的至少一个的无机材料层; 以及穿透无机材料层的穿透线，其中穿透线的一端电连接到线性导体的相应部分，而不会发生凹凸。

公开(公告)号：US20120159519A1

公开(公告)日：2012-06-21

申请号：US13288136

申请日：2011-11-03

Applicant: Yuichi Matsuda

Inventor： Yuichi Matsuda

IPC: G06F9/46

CPC classification number: G06F11/3003 ,  G06F11/0709 ,  G06F11/0754 ,  G06F11/3072 ,  G06F11/3089 ,  G06F2201/86 ,  G06F2201/865

Abstract: An event dependency management apparatus manages a first managed object at which a first event may occur, a second managed object at which a second event may occur in dependence upon the first event, and a third managed object at which a third event may occur in dependence upon the second event. The event dependency management apparatus includes a processor to calculate a difference between an occurrence time of the first event and an occurrence time of the third event, and determine that the third event has occurred in dependence upon the first event when the calculated difference is smaller than a predetermined time.

Abstract translation: 事件相关性管理装置管理可能发生第一事件的第一被管理对象，依赖于第一事件可能发生第二事件的第二被管理对象以及依赖于第三事件的第三被管理对象 在第二个事件。 事件相关性管理装置包括处理器，用于计算第一事件的发生时间和第三事件的发生时间之间的差异，并且当计算出的差值小于第三事件时，根据第一事件确定第三事件已经发生 一个预定的时间。

公开(公告)号：US08138609B2

公开(公告)日：2012-03-20

申请号：US12832177

申请日：2010-07-08

Applicant: Michio Horiuchi ,  Yasue Tokutake ,  Yuichi Matsuda ,  Tomoo Yamasaki ,  Yuta Sakaguchi

Inventor： Michio Horiuchi ,  Yasue Tokutake ,  Yuichi Matsuda ,  Tomoo Yamasaki ,  Yuta Sakaguchi

IPC: H01L23/48

CPC classification number: H01L21/561 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K1/185 ,  H05K3/4605 ,  H05K2201/0116 ,  H05K2201/09609 ,  H05K2201/09945 ,  H05K2201/10674 ,  H05K2203/0315 ,  H05K2203/1142 ,  H01L2924/00

Abstract: In a semiconductor device, a substrate includes a plurality of line conductors which penetrate the substrate from a top surface to a bottom surface of the substrate. A semiconductor chip is secured in a hole of the substrate. A first insulating layer is formed on the top surfaces of the substrate and the semiconductor chip. A first wiring layer is formed on the first insulating layer and electrically connected via through holes of the first insulating layer to the semiconductor chip and some line conductors exposed to one of the through holes. A second insulating layer is formed on the bottom surfaces of the substrate and the semiconductor chip. A second wiring layer is formed on the second insulating layer and electrically connected via a through hole of the second insulating layer to some line conductors exposed to the through hole.

Abstract translation: 在半导体器件中，衬底包括从衬底的顶表面到底表面穿透衬底的多个线导体。 半导体芯片固定在基板的孔中。 在衬底和半导体芯片的顶表面上形成第一绝缘层。 第一布线层形成在第一绝缘层上，并且经由第一绝缘层的通孔与半导体芯片电连接，一些线导体暴露于一个通孔。 在基板和半导体芯片的底面上形成第二绝缘层。 第二布线层形成在第二绝缘层上，并且经由第二绝缘层的通孔与暴露于通孔的一些线导体电连接。

公开(公告)号：US20110095433A1

公开(公告)日：2011-04-28

申请号：US12908943

申请日：2010-10-21

Applicant: Michio HORIUCHI ,  Yasue TOKUTAKE ,  Yuichi MATSUDA ,  Tsuyoshi KOBAYASHI ,  Tatsuaki DENDA

Inventor： Michio HORIUCHI ,  Yasue TOKUTAKE ,  Yuichi MATSUDA ,  Tsuyoshi KOBAYASHI ,  Tatsuaki DENDA

IPC: H01L23/535 ,  H05K1/02 ,  H01L21/768 ,  B05D5/12

CPC classification number: H05K3/323 ,  H01L24/00 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/29 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/83101 ,  H01L2224/838 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/0665 ,  H05K2201/09945 ,  H05K2201/10378 ,  H05K2203/0315 ,  H05K2203/1142 ,  H05K2203/1147 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2224/29199

Abstract: There is provided a method of manufacturing a conductive film. The method includes: (a) providing an anodized layer having a plurality of through holes extending therethrough in its thickness direction; (b) forming a plurality of linear conductors by filling each of the through holes with a conductive material; (c) forming protection layers on both surfaces of the anodized layer; (d) removing the anodized layer to form a plurality of gaps between the linear conductors; (e) forming an organic insulation layer between the protection layers to fill the gaps with the organic insulation layer; and (f) removing the protection layers.

Abstract translation: 提供了一种制造导电膜的方法。 该方法包括：（a）提供阳极氧化层，其具有在其厚度方向上延伸穿过其中的多个通孔; （b）通过用导电材料填充每个所述通孔来形成多个线性导体; （c）在阳极氧化层的两个表面上形成保护层; （d）去除所述阳极化层以在所述线状导体之间形成多个间隙; （e）在保护层之间形成有机绝缘层，以用有机绝缘层填充间隙; 和（f）去除保护层。

公开(公告)号：US06931724B2

公开(公告)日：2005-08-23

申请号：US10207259

申请日：2002-07-30

Applicant: Akio Rokugawa ,  Masayuki Sasaki ,  Yuichi Matsuda

Inventor： Akio Rokugawa ,  Masayuki Sasaki ,  Yuichi Matsuda

IPC: H01L23/12 ,  H01L23/498 ,  H05K1/11 ,  H05K3/00 ,  H05K3/04 ,  H05K3/10 ,  H05K3/20 ,  H05K3/38 ,  H05K3/46 ,  H01K3/10

CPC classification number: H05K3/4682 ,  H01L21/6835 ,  H01L23/49811 ,  H01L23/49822 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K1/113 ,  H05K3/007 ,  H05K3/045 ,  H05K3/108 ,  H05K3/20 ,  H05K3/205 ,  H05K3/388 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2203/0152 ,  H05K2203/0376 ,  H05K2203/0384 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49345

Abstract: A method of producing a multilayered substrate having: a first face being provided with pads bondable to electrode terminals of a semiconductor element, and a body containing a plurality of wiring line layers and insulation layers successively formed from the side of the multilayered substrate at which the face for mounting a semiconductor element is located, wherein the final insulating layer forms provides a second face of the multilayered substrate. The successive wiring line layers are connected by vias, and the second face has external connection terminal pads. The pads on the first face are formed on a metal sheet, a first layer of insulating material is formed on the metal sheet so as to cover the pads formed thereon, holes are formed through the insulating material to expose the end face of the pad, and a patterned metal layer is formed to provide a layer of wiring lines and vias connecting the pads with the wiring line on the layer of insulating material. Subsequently, layers of insulation material are formed to cover the layers of wiring lines, where vias are formed in the insulating material layers, and then patterned metal wiring line layers and filled vias are formed, until the predetermined number of sets of an insulation layer and a wiring line layer is obtained. The metal sheet is then removed.

Abstract translation: 一种多层基板的制造方法，其特征在于，具有：第一面，其具有可与半导体元件的电极端子连接的焊盘;以及主体，其包含从所述多层基板的一侧依次形成的多个布线层和绝缘层， 定位用于安装半导体元件的面，其中最终绝缘层形成提供多层基底的第二面。 连续的布线层通过通孔连接，第二面具有外部连接端子焊盘。 第一面上的焊盘形成在金属板上，在金属板上形成第一绝缘材料层，以覆盖形成在其上的焊盘，通过绝缘材料形成孔，露出焊盘的端面， 并且形成图案化金属层以提供将焊盘与绝缘材料层上的布线连接的布线线和通孔层。 随后，形成绝缘材料层以覆盖在绝缘材料层中形成通孔的布线层，然后形成图案化的金属布线层和填充的通孔，直到预定数量的绝缘层和 得到布线层。 然后去除金属片。

公开(公告)号：US5636206A

公开(公告)日：1997-06-03

申请号：US445397

申请日：1995-05-19

Applicant: Shigeo Amemiya ,  Yuichi Matsuda ,  Takao Ogura ,  Yasuki Fujii ,  Koji Tezuka ,  Hiromi Ueda ,  Hitoshi Uematsu

Inventor： Shigeo Amemiya ,  Yuichi Matsuda ,  Takao Ogura ,  Yasuki Fujii ,  Koji Tezuka ,  Hiromi Ueda ,  Hitoshi Uematsu

IPC: H04Q3/00 ,  H04J3/14

CPC classification number: H04J3/14

Abstract: An alarm masking system is provided which is capable of implementing alarm priority processing or alarm inhibit processing in ATM transmission equipment. In ATM transmission equipment, a received virtual path or virtual channel is switched by means of a switching unit and then sent to an interface unit. In doing this, if a higher priority alarm is detected or received at a reception side interface unit, an intra-office tag is added to the alarm cell and then it is output, so that by detecting this intra-office tag it is possible to inhibit generation of lower priority alarms in response to the higher order alarm.

Abstract translation: 提供一种能够在ATM传输设备中实现报警优先处理或报警禁止处理的报警屏蔽系统。 在ATM传输设备中，通过交换单元切换接收的虚拟路径或虚拟信道，然后发送到接口单元。 这样做时，如果在接收侧接口单元检测到或接收到较高优先级的报警，则向报警单元添加局内标签，然后输出，从而通过检测该室内标签， 响应高阶报警，禁止生成较低优先级的报警。

公开(公告)号：US5510515A

公开(公告)日：1996-04-23

申请号：US305962

申请日：1994-09-16

Applicant: Toshiyuki Akizawa ,  Hiroyuki Hasegawa ,  Hitoshi Nakamura ,  Katsufumi Urabe ,  Shingo Yoshida ,  Yuichi Matsuda ,  Tamiharu Sakai

Inventor： Toshiyuki Akizawa ,  Hiroyuki Hasegawa ,  Hitoshi Nakamura ,  Katsufumi Urabe ,  Shingo Yoshida ,  Yuichi Matsuda ,  Tamiharu Sakai

IPC: C07C51/43 ,  C07C57/07 ,  C07C67/52 ,  C07C231/24 ,  C07C67/48

CPC classification number: C07C231/24 ,  C07C51/43 ,  C07C67/52

Abstract: The present invention provides a process for purifying a polar vinyl compound, comprising pressurizing a crude polar vinyl compound containing impurities such as polymerization inhibiting substances and components of starting materials used in preparation of the polar vinyl compound to 500-3000 atm at 0.degree.-100.degree. C., the polar vinyl compound having at least one member selected from among oxygen, nitrogen and sulfur atoms, to thereby form crystals of the polar vinyl compound and separating the crystals of the polar vinyl compound from a liquid phase under pressure.

Abstract translation: 本发明提供一种极性乙烯基化合物的精制方法，其特征在于，在极限乙烯基化合物的制备中使用含有诸如聚合抑制物质和起始原料的杂质的粗极性乙烯基化合物在0〜100℃下加压至500-3000atm DEG，具有选自氧，氮和硫原子中的至少一种的极性乙烯基化合物，从而形成极性乙烯基化合物的晶体，并将极性乙烯基化合物的晶体在压力下从液相中分离出来。

公开(公告)号：US09460983B2

公开(公告)日：2016-10-04

申请号：US13613720

申请日：2012-09-13

Applicant: Michio Horiuchi ,  Yasue Tokutake ,  Yuichi Matsuda

Inventor： Michio Horiuchi ,  Yasue Tokutake ,  Yuichi Matsuda

IPC: H05K7/20 ,  H01L23/367 ,  H01L23/433 ,  H01L21/48 ,  H01L21/50 ,  H01L23/373

CPC classification number: H01L23/3677 ,  H01L21/4882 ,  H01L21/50 ,  H01L23/3733 ,  H01L23/3735 ,  H01L23/433 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/15311 ,  H05K7/2039 ,  H05K7/20509 ,  H01L2924/00

Abstract: A thermal interface material includes a metal foil, which has a first surface and an opposite second surface, and a plurality of rod conductors each having a side surface extending in a thickness direction of the metal foil. The rod conductors are arranged on at least one of the first and second surfaces of the metal foil in a planar direction that is perpendicular to the thickness direction. A resin layer covers at least the first surface and the second surface of the metal foil and the side surfaces of the rod conductors.

Abstract translation: 热界面材料包括金属箔，其具有第一表面和相对的第二表面，以及多个棒状导体，每个棒状导体的侧表面在金属箔的厚度方向上延伸。 棒状导体沿垂直于厚度方向的平面方向布置在金属箔的第一表面和第二表面中的至少一个上。 树脂层至少覆盖金属箔的第一表面和第二表面以及棒状导体的侧表面。

公开(公告)号：US09006586B2

公开(公告)日：2015-04-14

申请号：US13528987

申请日：2012-06-21

Applicant: Michio Horiuchi ,  Yasue Tokutake ,  Yuichi Matsuda ,  Tomoo Yamasaki

Inventor： Michio Horiuchi ,  Yasue Tokutake ,  Yuichi Matsuda ,  Tomoo Yamasaki

IPC: H05K1/11 ,  H01L21/48 ,  H01L23/498 ,  H05K3/46

CPC classification number: H01L21/486 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/4602 ,  H05K2201/10378 ,  Y10T29/49124 ,  H01L2924/00

Abstract: One embodiment provides a wiring substrate including: a core substrate having an insulative base member, the insulative base member having a first surface and a second surface, a plurality of linear conductors penetrating through the insulative base member from the first surface to the second surface; an inorganic material layer joined to at least one of the first surface and the second surface of the insulative base member; and a penetration line penetrating through the inorganic material layer, wherein one end of the penetration line is electrically connected to a corresponding part of the linear conductors, without intervention of a bump.

Abstract translation: 一个实施例提供一种布线基板，包括：具有绝缘基底构件的芯基板，所述绝缘基底构件具有第一表面和第二表面;多个线状导体，从所述第一表面穿过所述绝缘基底构件到所述第二表面; 连接到所述绝缘基体的第一表面和所述第二表面中的至少一个的无机材料层; 以及穿透无机材料层的穿透线，其中穿透线的一端电连接到线性导体的相应部分，而不会发生凹凸。