-
公开(公告)号:US11380536B2
公开(公告)日:2022-07-05
申请号:US16867554
申请日:2020-05-05
Applicant: Applied Materials, Inc.
Inventor: Xi Cen , Yakuan Yao , Yiming Lai , Kai Wu , Avgerinos V. Gelatos , David T. Or , Kevin Kashefi , Yu Lei , Lin Dong , He Ren , Yi Xu , Mehul Naik , Hao Chen , Mang-Mang Ling
IPC: H01L21/02 , H01L21/67 , H01L21/768
Abstract: Methods for pre-cleaning substrates having metal and dielectric surfaces are described. The substrate is exposed to a strong reductant to remove contaminants from the metal surface and damage the dielectric surface. The substrate is then exposed to an oxidation process to repair the damage to the dielectric surface and oxidize the metal surface. The substrate is then exposed to a weak reductant to reduce the metal oxide to a pure metal surface without substantially affecting the dielectric surface. Processing tools and computer readable media for practicing the method are also described.
-
公开(公告)号:US11245022B2
公开(公告)日:2022-02-08
申请号:US16876276
申请日:2020-05-18
Applicant: Applied Materials, Inc.
Inventor: Yongjing Lin , Karla M. Bernal Ramos , Luping Li , Shih Chung Chen , Jacqueline S. Wrench , Yixiong Yang , Steven C. H. Hung , Srinivas Gandikota , Naomi Yoshida , Lin Dong
Abstract: Methods of forming and processing semiconductor devices are described. Certain embodiments related to electronic devices which comprise a dipole region having an interlayer dielectric, a high-κ dielectric material, and a dipole layer. The dipole layer comprises one or more of titanium lanthanum nitride (TiLaN), titanium yttrium nitride (TiYN), titanium strontium nitride (TiSrN), titanium magnesium nitride (TiMgN, titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN), hafnium carbide (HfC), hafnium nitride (HfN), hafnium oxynitride (HfON), hafnium oxycarbide (HfOC), hafnium carbide aluminum (HfCAl), hafnium aluminum nitride (HfAlN), or hafnium carbonitride (HfCN).
-
公开(公告)号:US11075276B2
公开(公告)日:2021-07-27
申请号:US16594596
申请日:2019-10-07
Applicant: APPLIED MATERIALS, INC.
Inventor: Yongjing Lin , Shih Chung Chen , Naomi Yoshida , Lin Dong , Liqi Wu , Rongjun Wang , Steven Hung , Karla Bernal Ramos , Yixiong Yang , Wei Tang , Sang-Ho Yu
IPC: H01L29/49 , H01L29/40 , H01L21/285 , H01L21/02
Abstract: Methods and apparatus for forming a semiconductor structure such as an NMOS gate electrode are described. Methods may include depositing a first capping layer having a first surface atop a first surface of a high-k dielectric layer; and depositing at least one metal layer having a first surface atop the first surface of the first capping layer, wherein the at least one metal layer includes titanium aluminum silicide material. Some methods include removing an oxide layer from the first surface of the first capping layer by contacting the first capping layer with metal chloride in an amount sufficient to remove an oxide layer. Some methods for depositing a titanium aluminum silicide material are performed by an atomic layer deposition process performed at a temperature of 350 to 400 degrees Celsius.
-
公开(公告)号:US10665450B2
公开(公告)日:2020-05-26
申请号:US16104352
申请日:2018-08-17
Applicant: APPLIED MATERIALS, INC.
Inventor: Yixiong Yang , Paul F. Ma , Wei V. Tang , Wenyu Zhang , Shih Chung Chen , Chen Han Lin , Chi-Chou Lin , Yi Xu , Yu Lei , Naomi Yoshida , Lin Dong , Siddarth Krishnan
Abstract: Methods and apparatus for forming a semiconductor structure, including depositing a doping stack having a first surface atop a high-k dielectric layer, wherein the doping stack includes at least one first metal layer having a first surface, at least one second metal layer comprising a first aluminum dopant and a first surface, wherein the second metal layer is atop the first surface of the first metal layer, and at least one third metal layer atop the first surface of the second metal layer; depositing an anneal layer atop the first surface of the doping stack; annealing the structure to diffuse at least the first aluminum dopant into the high-k dielectric layer; removing the anneal layer; and depositing at least one work function layer atop the first surface of the doping stack.
-
公开(公告)号:US20190019874A1
公开(公告)日:2019-01-17
申请号:US16033880
申请日:2018-07-12
Applicant: Applied Materials, Inc.
Inventor: Paul F. Ma , Seshadri Ganguli , Shih Chung Chen , Rajesh Sathiyanarayanan , Atashi Basu , Lin Dong , Naomi Yoshida , Sang Ho Yu , Liqi Wu
Abstract: Film stacks and methods of forming film stacks including a high-k dielectric layer on a substrate, a high-k capping layer on the high-k dielectric layer, an n-metal layer on the high-k capping layer and an n-metal capping layer on the n-metal layer. The n-metal layer having an aluminum rich interface adjacent the high-k capping layer.
-
26.
公开(公告)号:US09748354B2
公开(公告)日:2017-08-29
申请号:US15043883
申请日:2016-02-15
Applicant: APPLIED MATERIALS, INC.
Inventor: Wei V. Tang , Paul F. Ma , Steven C. H. Hung , Michael Chudzik , Siddarth Krishnan , Wenyu Zhang , Seshadri Ganguli , Naomi Yoshida , Lin Dong , Yixiong Yang , Liqi Wu , Shih Chung Chen
CPC classification number: H01L29/66446 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/78603 , H01L29/78681
Abstract: Semiconductor devices incorporating multi-threshold voltage structures and methods of forming such semiconductor devices are provided herein. In some embodiments of the present disclosure, a semiconductor device having a multi-threshold voltage structure includes: a substrate; a gate dielectric layer atop the substrate, wherein the gate dielectric layer comprises an interface layer and a high-k dielectric layer atop the interface layer; a lanthanum nitride layer deposited atop the high-k dielectric layer; an interface of the interface layer and the high-k dielectric layer comprising lanthanum species from the lanthanum nitride layer; and a gate electrode layer atop the lanthanum nitride layer.
-
公开(公告)号:US09673277B2
公开(公告)日:2017-06-06
申请号:US14885521
申请日:2015-10-16
Applicant: APPLIED MATERIALS, INC.
Inventor: Adam Brand , Bingxi Sun Wood , Naomi Yoshida , Lin Dong , Shiyu Sun , Chi-Nung Ni , Yihwan Kim
IPC: H01L29/06 , H01L29/20 , H01L29/66 , H01L21/762 , H01L21/306
CPC classification number: H01L29/0673 , H01L21/30612 , H01L21/76224 , H01L29/20 , H01L29/42392 , H01L29/66522 , H01L29/66545 , H01L29/66795 , H01L29/78696
Abstract: A method of forming a semiconductor device includes: forming a superlattice structure atop the top surface of a substrate, wherein the superlattice structure comprises a plurality of first layers and a corresponding plurality of second layers alternatingly arranged in a plurality of stacked pairs; forming a lateral etch stop layer by epitaxial deposition of a material of the first layer or the second layer of the superlattice structure atop a sidewall of the superlattice structure, or by selectively oxidizing edges of the first layers and second layers of the superlattice structure; subsequently forming a source region adjacent a first end of the superlattice structure and a drain region adjacent a second opposing end of the superlattice structure; and selectively etching the superlattice structure to remove each of the first layers or each of the second layers to form a plurality of voids in the superlattice structure.
-
-
-
-
-
-